soc-design

Here are 24 public repositories matching this topic...

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds

Updated Sep 15, 2025
Python

arm-university / Advanced-System-on-Chip-Design-Education-Kit

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Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description and software programming languages

arm fpga armv7 hardware-designs cortex-a amba cortex-a9 arm-cortex-a9 soc-design system-on-chip-design zybo-z7-10

Updated Oct 7, 2025
HTML

arm-university / Fundamentals-of-System-on-Chip-Design-on-Arm-Cortex-M-Microcontrollers

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A textbook on understanding system on chip design

fpga embedded-systems textbook cmsis soc fpga-soc trustzone amba cpu-architecture arm-cortex-m soc-design system-on-chip-design bus-architecture

Updated Jun 16, 2025

arm-university / Modern-System-on-Chip-Design-on-Arm

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A textbook on system on chip design using Arm Cortex-A

textbook hardware-designs computer-architecture soc fpga-soc system-design soc-design system-on-chip-design arm-cortex-a

Updated Jun 11, 2025

arm-university / System-on-Chip-Design-with-Arm-Cortex-M-Processors

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A reference book on System-on-Chip Design

cortex-m embedded-systems software-design amba arm-cortex-m soc-design keil-mdk system-on-chip-design bus-architecture cortex-m-processors reference-book

Updated Jun 16, 2025

nekosilverfox / ZYNQ

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⚙️ 基于 Zynq-7 全可编程 SoC 的设计

sdk fpga zynq verilog xilinx vivado zynq-7010 zynq-7000 soc-fpga zynq-7020 soc-design

Updated Dec 31, 2021
HTML

RISMicroDevices / OpenNCB

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Open-source Non-coherent CHI Bridge (CHI SN-F to AXI-4 bridge)

bus chisel chisel3 soc chi axi amba protocol-converter axi4 amba-axi soc-design amba-chi protocol-bridge

Updated Oct 9, 2024
Scala

Vor-Art / DCD_MultiBankMemory

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SystemVerilog implementation of a multi-bank memory as part of "[F23] Digital Circuit Design" course

fpga throughput systemverilog innopolis-university soc-design multibank-memory

Updated Dec 19, 2023
SystemVerilog

williaml33moore / bathtub

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BDD Gherkin implementation in native SystemVerilog, based on UVM.

asic fpga bdd bdd-specs rtl verilog systemverilog uvm verilog-hdl bdd-framework asic-verification design-verification asic-design rtl-design soc-design soc-verification uvm-verification

Updated Nov 16, 2024
SystemVerilog

iamstan13y / fomalhaut-microservices

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bootstrap docker redis mongodb postgresql web-api asp-net-core dapper grpc-service microservices-architecture solid-principles fluentvalidation rabbit-mq mediator-pattern razor-pages cqrs-pattern soc-design aggregator-services ocelot-api-gateway

Updated May 9, 2024
C#

Entries for the 2023 5th National College Student Integrated Circuit EDA Elite Challenge. SoC chip physical layout static IR drop prediction project based on methods such as image processing and NLP unsupervised learning.

machine-learning word2vec cnn power-network unsupervised-learning pix2pix vlsi-physical-design signoff u-net electronic-design-automation soc-design u-net-pytorch physical-layout-analysis ir-drop

Updated Aug 12, 2024
Python

amitops2103 / NASSCOM_VSD_SoC_Physical_Design_Program

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Digital VLSI Soc-Physical Design (Picorv32)

vlsi-physical-design soc-design physical-layout-analysis

Updated Sep 17, 2024

trustfarm / TFSDxr-Neuron-Quantization

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Humans respond more to **relative change (difference)** and **events (extrema/saturation)** than absolute levels. TFSDxr‑Neuron‑Quantization [TimeFeedBackSigmaDelta 4 eXtensible Reality] maps this principle into digital logic for **low‑power, event‑based encoding**.

ai scalable fpga codec neuron quantization neuromorphic gemm scalable-machine-learning soc-design

Updated Oct 17, 2025

WARE-dev750 / soc-software

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Advanced Endpoint Forensic & Observability Framework | C++20 Windows Internals Hunter

malware-analysis edr windows-internals soc-tools soc-design soc-analyst

Updated Dec 26, 2025
C++

RupamBora-ASIC / rupambora_RISC-V-SoC-Reference-Tapout-Program_VSD

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This repository documents my journey in the RISC-V Reference SoC Tapeout Program. The first 10 weeks focus on RTL design, synthesis, simulation, and verification using open-source tools like Yosys, Icarus Verilog, GTKWave, and OpenLane, building a foundation for full-chip tapeout.

risc-v tapeout physical-design open-source-eda soc-design rtl-to-gdsii

Updated Oct 4, 2025

rehanmq / asic-soc-ml-accelerator-verification

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End-to-end ASIC SoC design and functional verification of a lightweight machine learning accelerator using SystemVerilog and UVM. Includes Python automation for test generation and result analysis. Built to simulate real-world ML silicon validation at scale.

systemverilog msp432 system-design verilator asic-verification soc-design ai-hardware