Add SOF support for M7 core on NXP i.MX8MP

app/boards/imx8mp_evk_mimx8ml8_m7_ddr.conf

@@ -0,0 +1,12 @@
+CONFIG_IMX8M_CM7=y
+CONFIG_ZEPHYR_NATIVE_DRIVERS=y
+CONFIG_SHARED_INTERRUPTS=y
+CONFIG_CLOCK_CONTROL_FIXED_RATE_CLOCK=y
+CONFIG_ROMSTART_RELOCATION_ROM=y
+CONFIG_DMA_NXP_SOF_HOST_DMA_ALIGN=32
+CONFIG_DMA=y
+CONFIG_DMA_NXP_SDMA=y
+CONFIG_DAI_NXP_SAI=y
+CONFIG_SAI_HAS_MCLK_CONFIG_OPTION=y
+CONFIG_COMP_ASRC=n
+

app/boards/imx8mp_evk_mimx8ml8_m7_ddr.overlay

@@ -0,0 +1,27 @@
+/*
+ * Copyright 2026 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	host_dma: dma {
+		compatible = "nxp,sof-host-dma";
+		dma-channels = <32>;
+		#dma-cells = <0>;
+	};
+};
+
+&sdma3 {
+	status = "okay";
+};
+
+&sai3 {
+	pinctrl-0 = <&sai3_default>;
+	pinctrl-names = "default";
+	rx-fifo-watermark = <64>;
+	tx-fifo-watermark = <64>;
+	fifo-depth = <96>;
+	rx-sync-mode = <1>;
+	status = "okay";
+};

scripts/xtensa-build-zephyr.py

@@ -217,6 +217,10 @@ class PlatformConfig:
 		"hifi4_mscale_v2_0_2_prod",
 		RIMAGE_KEY = "key param ignored by imx8m"
 	),
+	"imx8m_cm7" : PlatformConfig(
+		"imx", "imx8mp_evk/mimx8ml8/m7/ddr",
+		"", "", "", ""
+	),
 	"imx8ulp" : PlatformConfig(
 		"imx", "imx8ulp_evk/mimx8ud7/adsp",
 		f"RI-2023.11{xtensa_tools_version_postfix}",
@@ -1295,7 +1299,7 @@ def gzip_compress(fname, gzdst=None):
 # Don't run sof_ri_info and ignore silently .ri files that don't have one.
 RI_INFO_UNSUPPORTED = []
 
-RI_INFO_UNSUPPORTED += ['imx8', 'imx8x', 'imx8m', 'imx8ulp', 'imx95']
+RI_INFO_UNSUPPORTED += ['imx8', 'imx8x', 'imx8m', 'imx8m_cm7', 'imx8ulp', 'imx95']
 RI_INFO_UNSUPPORTED += ['rn', 'acp_6_0']
 RI_INFO_UNSUPPORTED += ['mt8186', 'mt8188', 'mt8195', 'mt8196', 'mt8365']
 

src/platform/Kconfig

@@ -145,6 +145,15 @@ config IMX8M
 	help
 	  Select if your target platform is imx8m-compatible
 
+config IMX8M_CM7
+	bool "Build for NXP i.MX8MP CM7 core"
+	select ZEPHYR_LOG
+	select BUILD_OUTPUT_BIN
+	select HOST_PTABLE
+	select IMX
+	help
+	  Select if your target platform is imx8mp-compatible with cm7 core.
+
 config IMX8ULP
 	bool "Build for NXP i.MX8ULP"
 	select XT_HAVE_RESET_VECTOR_ROM

src/platform/imx8m_cm7/include/platform/lib/clk.h

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright 2026 NXP
+ */
+
+#ifdef __SOF_LIB_CLK_H__
+
+#ifndef __PLATFORM_LIB_CLK_H__
+#define __PLATFORM_LIB_CLK_H__
+
+#define CLK_MAX_CPU_HZ 800000000
+#define CPU_DEFAULT_IDX 0
+#define NUM_CPU_FREQ 1
+#define NUM_CLOCKS 1
+
+struct sof;
+
+void platform_clock_init(struct sof *sof);
+
+#endif /* __PLATFORM_LIB_CLK_H__ */
+
+#else
+
+#error "This file shouldn't be included from outside of sof/lib/clk.h"
+
+#endif /* __SOF_LIB_CLK_H__ */

src/platform/imx8m_cm7/include/platform/lib/dma.h

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright 2026 NXP
+ */
+
+#ifdef __SOF_LIB_DMA_H__
+
+#ifndef __PLATFORM_LIB_DMA_H__
+#define __PLATFORM_LIB_DMA_H__
+
+/* TODO: remove me whenever possible */
+
+#endif /* __PLATFORM_LIB_DMA_H__ */
+
+#else
+
+#error "This file shouldn't be included from outside of sof/lib/dma.h"
+
+#endif /* __SOF_LIB_DMA_H__ */

src/platform/imx8m_cm7/include/platform/lib/mailbox.h

@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright 2026 NXP
+ */
+
+#ifdef __SOF_LIB_MAILBOX_H__
+
+#ifndef __PLATFORM_LIB_MAILBOX_H__
+#define __PLATFORM_LIB_MAILBOX_H__
+
+/* The i.MX8MP CM7 mailbox region is organized like this:
+ *
+ * +---------------+-------------------------+
+ * | Region name   | Base address  |  Size   |
+ * +---------------+---------------+---------+
+ * | Outbox region |   0x82000000  | 0x1000  |
+ * +---------------+---------------+---------+
+ * | Inbox region  |   0x82001000  | 0x1000  |
+ * +---------------+---------------+---------+
+ * | Stream region |   0x82002000  | 0x1000  |
+ * +---------------+---------------+---------+
+ *
+ * IMPORTANT: all regions should be 32-byte aligned.
+ * This is required because cache maintenance might
+ * be performed on them.
+ */
+
+/* outbox */
+#define MAILBOX_DSPBOX_SIZE 0x1000
+#define MAILBOX_DSPBOX_BASE 0x82000000
+#define MAILBOX_DSPBOX_OFFSET 0
+
+/* inbox */
+#define MAILBOX_HOSTBOX_SIZE 0x1000
+#define MAILBOX_HOSTBOX_BASE 0x82001000
+#define MAILBOX_HOSTBOX_OFFSET (MAILBOX_DSPBOX_OFFSET + MAILBOX_DSPBOX_SIZE)
+
+/* stream */
+#define MAILBOX_STREAM_SIZE 0x1000
+#define MAILBOX_STREAM_BASE 0x82002000
+#define MAILBOX_STREAM_OFFSET (MAILBOX_HOSTBOX_OFFSET + MAILBOX_HOSTBOX_SIZE)
+
+#endif /* __PLATFORM_LIB_MAILBOX_H__ */
+
+#else
+
+#error "This file shouldn't be included from outside of sof/lib/mailbox.h"
+
+#endif /* __SOF_LIB_MAILBOX_H__ */

src/platform/imx8m_cm7/include/platform/lib/memory.h

@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright 2026 NXP
+ */
+
+#ifdef __SOF_LIB_MEMORY_H__
+
+#ifndef __PLATFORM_LIB_MEMORY_H__
+#define __PLATFORM_LIB_MEMORY_H__
+
+#include <rtos/cache.h>
+
+#define PLATFORM_DCACHE_ALIGN DCACHE_LINE_SIZE
+
+#define SHARED_DATA
+
+#define uncache_to_cache(address) address
+#define cache_to_uncache(address) address
+#define cache_to_uncache_init(address) address
+#define is_uncached(address) 0
+
+/* no address translation required */
+#define host_to_local(addr) (addr)
+#define local_to_host(addr) (addr)
+
+#define HEAPMEM_SIZE 0x00010000
+
+/* WAKEUP domain MU1 side B */
+#define MU_BASE 0x30AB0000UL
+
+static inline void *platform_shared_get(void *ptr, int bytes)
+{
+	return ptr;
+}
+
+#endif /* __PLATFORM_LIB_MEMORY_H__ */
+
+#else
+
+#error "This file shouldn't be included from outside of sof/lib/memory.h"
+
+#endif /* __SOF_LIB_MEMORY_H__*/

src/platform/imx8m_cm7/include/platform/platform.h

@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright 2026 NXP
+ */
+
+#ifdef __SOF_PLATFORM_H__
+
+#ifndef __PLATFORM_PLATFORM_H__
+#define __PLATFORM_PLATFORM_H__
+
+/* refers to M7 core clock - one core, one clock */
+#define PLATFORM_DEFAULT_CLOCK 0
+
+#define HOST_PAGE_SIZE 4096
+
+#define PLATFORM_PAGE_TABLE_SIZE 256
+
+/* TODO: generous (SOF is usually used with 2 channels at most on i.MX
+ * platforms) and (potentially) not true. Can be adjusted later on if
+ * need be.
+ */
+#define PLATFORM_MAX_CHANNELS 4
+/* TODO: same as PLATFORM_MAX_CHANNELS */
+#define PLATFORM_MAX_STREAMS 5
+
+/* WAKEUP domain MU7 side B */
+#define PLATFORM_IPC_INTERRUPT 97
+
+#endif /* __PLATFORM_PLATFORM_H__ */
+
+#else
+
+#error "This file shouldn't be included from outside of sof/platform.h"
+
+#endif /* __SOF_PLATFORM_H__ */

src/platform/imx8m_cm7/include/platform/trace/trace.h

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright 2026 NXP
+ */
+
+#ifdef __SOF_TRACE_TRACE_H__
+
+#ifndef __PLATFORM_TRACE_TRACE_H__
+#define __PLATFORM_TRACE_TRACE_H__
+
+/* TODO: remove me whenever possible */
+
+#endif /* __PLATFORM_TRACE_TRACE_H__ */
+
+#else
+
+#error "This file shouldn't be included from outside of sof/trace/trace.h"
+
+#endif /* __SOF_TRACE_TRACE_H__ */

src/platform/imx8m_cm7/lib/clk.c

@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2026 NXP
+ */
+
+#include <rtos/clk.h>
+#include <sof/lib/notifier.h>
+
+static const struct freq_table platform_cpu_freq[] = {
+	{
+		.freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
+		.ticks_per_msec = CONFIG_SYS_CLOCK_TICKS_PER_SEC * 1000,
+	},
+};
+
+static struct clock_info platform_clocks_info[NUM_CLOCKS];
+
+void platform_clock_init(struct sof *sof)
+{
+	int i;
+
+	sof->clocks = platform_clocks_info;
+
+	for (i = 0; i < CONFIG_CORE_COUNT; i++) {
+		sof->clocks[i] = (struct clock_info) {
+			.freqs_num = NUM_CPU_FREQ,
+			.freqs = platform_cpu_freq,
+			.default_freq_idx = CPU_DEFAULT_IDX,
+			.current_freq_idx = CPU_DEFAULT_IDX,
+			.notification_id = NOTIFIER_ID_CPU_FREQ,
+			.notification_mask = NOTIFIER_TARGET_CORE_MASK(i),
+			.set_freq = NULL,
+		};
+	}
+}

src/platform/imx8m_cm7/linker/data-sections.ld

@@ -0,0 +1,5 @@
+SECTION_PROLOGUE(.fw_metadata,,)
+{
+	KEEP (*(*.fw_metadata))
+	. = ALIGN(16);
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)