zephyr: alloc: calculate L3 heap size based on actual IMR size#10173
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kv2019i merged 2 commits intothesofproject:mainfrom Nov 27, 2025
Merged
zephyr: alloc: calculate L3 heap size based on actual IMR size#10173kv2019i merged 2 commits intothesofproject:mainfrom
kv2019i merged 2 commits intothesofproject:mainfrom
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abonislawski
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Pull Request Overview
Updates L3 heap management to dynamically calculate heap size from hardware IMR registers instead of using hardcoded values, and adds conditional initialization based on IMR availability.
- Replaces hardcoded IMR_L3_HEAP_SIZE with dynamic calculation using ace_imr_get_mem_size()
- Adds conditional L3 heap initialization that only occurs when IMR is actually used
- Includes MMU memory mapping for the L3 heap when CONFIG_MMU is enabled
Reviewed Changes
Copilot reviewed 2 out of 2 changed files in this pull request and generated 2 comments.
| File | Description |
|---|---|
| zephyr/lib/alloc.c | Updates L3 heap size calculation and adds conditional initialization with MMU support |
| west.yml | Updates Zephyr revision to pull request branch |
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af974c307477 soc: intel_adsp: ace: add IMR info registers 35a1e62035fd soc: intel_adsp: ace40: extend hwreg1 MMU mapping Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Updates the L3 heap management to dynamically calculate heap size based on the actual IMR size reported by hardware registers instead of using hardcoded values. Only initializes the L3 heap when the IMR is actually available and being used, as determined by the ace_imr_used() function, improving robustness by preventing the initialization of unavailable memory regions. Adds proper memory mapping when MMU is enabled, which maps the physical L3 heap memory to a virtual address with appropriate permissions (read/write with write-back caching). MMU mapping is required because it is no longer a fixed region with fixed mapping in Zephyr. This change makes the L3 heap allocation more flexible and adaptable to different hardware configurations. Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
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Rebase + west commit update (Zephyr PR is merged) |
lgirdwood
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Nov 25, 2025
lyakh
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| void *cached_ptr = sys_cache_cached_ptr_get(l3_heap_start); | ||
| uintptr_t va = POINTER_TO_UINT(cached_ptr); | ||
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| arch_mem_map(l3_heap_start, va, l3_heap_size, K_MEM_PERM_RW | K_MEM_CACHE_WB); |
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btw, why not sys_mm_drv_map_region()?
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They are not equivalent, just like the lib/llext manager - we are using both of them. In short, the MM TLB driver is for SRAM memory. I assume in the future we will get some nicer API instead of arch_mem_map.
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sof-ci/jenkins/pr-build failing on TGL because this zephyr version is no longer compatible with TGL |
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serhiy-katsyuba-intel
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Nov 26, 2025
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SOFCI TEST |
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Nov 27, 2025
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Updates the L3 heap management to dynamically calculate heap size based on the actual IMR size reported by hardware registers instead of using hardcoded values.
Only initializes the L3 heap when the IMR is actually available and being used, as determined by the ace_imr_used() function.
This change makes the L3 heap allocation more flexible and adaptable to different hardware configurations.