mailbox: qcom-apcs-ipc-mailbox: Add compatible string

Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml

@@ -0,0 +1,138 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,qcs8300-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Shikra TLMM block
+
+maintainers:
+  - Komal Bajaj <komal.bajaj@oss.qualcomm.com>
+
+description: |
+  Top Level Mode Multiplexer pin controller in Qualcomm Shikra SoC.
+
+allOf:
+  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+  compatible:
+    const: qcom,shikra-tlmm
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  gpio-reserved-ranges:
+    minItems: 1
+    maxItems: 83
+
+  gpio-line-names:
+    maxItems: 166
+
+patternProperties:
+  "-state$":
+    oneOf:
+      - $ref: "#/$defs/qcom-shikra-tlmm-state"
+      - patternProperties:
+          "-pins$":
+            $ref: "#/$defs/qcom-shikra-tlmm-state"
+        additionalProperties: false
+
+$defs:
+  qcom-shikra-tlmm-state:
+    type: object
+    description:
+      Pinctrl node's client devices use subnodes for desired pin configuration.
+      Client device subnodes use below standard properties.
+    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
+    unevaluatedProperties: false
+
+    properties:
+      pins:
+        description:
+          List of gpio pins affected by the properties specified in this
+          subnode.
+        items:
+          oneOf:
+            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2])$"
+            - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
+        minItems: 1
+        maxItems: 36
+
+      function:
+        description:
+          Specify the alternative function to be configured for the specified
+          pins.
+
+        enum: [ gpio, agera_pll, atest_bbrx, atest_char, atest_char_start,
+          atest_gpsadc, atest_tsens, atest_tsens2, atest_usb, cam_mclk,
+          cci_async_in0, cci_i2c_scl0, cci_i2c_scl1, cci_i2c_sda0,
+          cci_i2c_sda1, cci_timer, char_exec_pending, char_exec_release,
+          cri_trng, cri_trng0, cri_trng1, dac_calib, dbg_out_clk,
+          ddr_bist_complete, ddr_bist_fail, ddr_bist_start, ddr_bist_stop,
+          ddr_pxi0, ddr_pxi1, dmic0_clk, dmic0_data, dmic1_clk, dmic1_data,
+          emac0_dll, emac0_mcg0, emac0_mcg1, emac0_mcg2, emac0_mcg3,
+          emac0_phy, emac0_ptp, emac1_dll, emac1_mcg0, emac1_mcg1,
+          emac1_mcg2, emac1_mcg3, emac1_phy, emac1_ptp, ext_mclk, gcc_gp1,
+          gcc_gp2, gcc_gp3, gsm0_tx, i2s0_clk, i2s0_data0, i2s0_data1,
+          i2s0_data2, i2s0_data3, i2s0_ws, i2s1_clk, i2s1_data0, i2s1_data1,
+          i2s1_ws, i2s2_clk, i2s2_data0, i2s2_data1, i2s2_ws, i2s3_clk,
+          i2s3_data0, i2s3_data1, i2s3_ws, jitter_bist, m_voc, mdp_vsync,
+          mdp_vsync_e, mdp_vsync_p, mdp_vsync_s, mpm_pwr, mss_lte, nav_gpio,
+          pa_indicator_or, pbs_in, pbs_out, pcie0_clk_req_n, phase_flag,
+          pll_bist, pll_bypassnl, pll_clk, pll_reset_n, prng_rosc, pwm_0,
+          pwm_1, pwm_2, pwm_3, pwm_4, pwm_5, pwm_6, pwm_7, pwm_8, pwm_9,
+          qdss_cti, qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4,
+          qup0_se5, qup0_se6, qup0_se7, qup0_se8, qup0_se9, rgmii0_mdc,
+          rgmii0_mdio, rgmii0_rx_ctl, rgmii0_rxc, rgmii0_rxd0, rgmii0_rxd1,
+          rgmii0_rxd2, rgmii0_rxd3, rgmii0_tx_ctl, rgmii0_txc, rgmii0_txd0,
+          rgmii0_txd1, rgmii0_txd2, rgmii0_txd3, rgmii1_mdc, rgmii1_mdio,
+          rgmii1_rx_ctl, rgmii1_rxc, rgmii1_rxd0, rgmii1_rxd1, rgmii1_rxd2,
+          rgmii1_rxd3, rgmii1_tx_ctl, rgmii1_txc, rgmii1_txd0, rgmii1_txd1,
+          rgmii1_txd2, rgmii1_txd3, sd_write_protect, sdc1_tb_trig,
+          sdc2_tb_trig, ssbi_wtr0, ssbi_wtr1, ssbi_wtr2, ssbi_wtr3,
+          swr0_rx_clk, swr0_rx_data0, swr0_rx_data1, swr0_tx_clk,
+          swr0_tx_data0, tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout,
+          tgu_ch3_trigout, tsc_async, tsense_pwm, uim1_clk, uim1_data,
+          uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present,
+          uim2_reset, unused_adsp, unused_gsm1, usb0_phy_ps, vfr_1,
+          vsense_trigger_mirnat, wlan1_adc0, wlan1_adc1 ]
+
+    required:
+      - pins
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    tlmm: pinctrl@500000 {
+        compatible = "qcom,shikra-tlmm";
+        reg = <0x00500000 0x800000>;
+
+        interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+
+        gpio-controller;
+        #gpio-cells = <2>;
+
+        interrupt-controller;
+        #interrupt-cells = <2>;
+
+        gpio-ranges = <&tlmm 0 0 166>;
+
+        qup-uart0-default-state {
+            pins = "gpio0", "gpio1";
+            function = "qup0_se1";
+            drive-strength = <2>;
+            bias-disable;
+        };
+    };
+...

drivers/mailbox/qcom-apcs-ipc-mailbox.c

@@ -53,6 +53,10 @@ static const struct qcom_apcs_ipc_data sdx55_apcs_data = {
 	.offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk"
 };
 
+static const struct qcom_apcs_ipc_data shikra_apcs_data = {
+	.offset = 12, .clk_name = NULL
+};
+
 static const struct regmap_config apcs_regmap_config = {
 	.reg_bits = 32,
 	.reg_stride = 4,
@@ -169,6 +173,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = {
 	{ .compatible = "qcom,sc7180-apss-shared", .data = &apps_shared_apcs_data },
 	{ .compatible = "qcom,sc8180x-apss-shared", .data = &apps_shared_apcs_data },
 	{ .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data },
+	{ .compatible = "qcom,shikra-apcs-hmss-global", .data = &shikra_apcs_data },
 	{}
 };
 MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);

drivers/pinctrl/qcom/Kconfig.msm

@@ -341,6 +341,14 @@ config PINCTRL_SDX75
          Qualcomm Technologies Inc TLMM block found on the Qualcomm
          Technologies Inc SDX75 platform.
 
+config PINCTRL_SHIKRA
+	tristate "Qualcomm Technologies Inc Shikra pin controller driver"
+	depends on ARM64 || COMPILE_TEST
+	help
+	  This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+	  Qualcomm Technologies Inc TLMM block found on the Qualcomm
+	  Technologies Inc Shikra platform.
+
 config PINCTRL_SM4450
 	tristate "Qualcomm Technologies Inc SM4450 pin controller driver"
 	depends on ARM64 || COMPILE_TEST

drivers/pinctrl/qcom/Makefile

@@ -52,6 +52,7 @@ obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
 obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o
 obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o
 obj-$(CONFIG_PINCTRL_SDX75) += pinctrl-sdx75.o
+obj-$(CONFIG_PINCTRL_SHIKRA) += pinctrl-shikra.o
 obj-$(CONFIG_PINCTRL_SM4250_LPASS_LPI) += pinctrl-sm4250-lpass-lpi.o
 obj-$(CONFIG_PINCTRL_SM4450) += pinctrl-sm4450.o
 obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o