Skip to content

Revert the v2 patch glymur-crd: Enable eDP display support and "Describe display related nodes" and applied the latest patch v3 #775

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
naala-qcom wants to merge 4 commits into
base: tech/all/dt/glymur
Choose a base branch
from
Open

Revert the v2 patch glymur-crd: Enable eDP display support and "Describe display related nodes" and applied the latest patch v3 #775

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
4 commits
Select commit Hold shift + click to select a range
53cdefa
Revert "PENDING: arm64: dts: qcom: glymur: Describe display related n…
Mar 10, 2026
4590030
Revert "PENDING: arm64: dts: qcom: glymur-crd: Enable eDP display"
naala-qcom Mar 9, 2026
a239838
FROMLIST: arm64: dts: qcom: glymur: Describe display related nodes
naala-qcom Mar 9, 2026
2b16cc0
FROMLIST: arm64: dts: qcom: glymur-crd: Enable eDP display support
naala-qcom Mar 9, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
34 changes: 17 additions & 17 deletions arch/arm64/boot/dts/qcom/glymur-crd.dts
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -153,37 +153,37 @@
};
};

vreg_edp_3p3: regulator-edp-3p3 {
vreg_misc_3p3: regulator-misc-3p3 {
compatible = "regulator-fixed";

regulator-name = "VREG_EDP_3P3";
regulator-name = "VREG_MISC_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;

gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
gpio = <&pmh0110_f_e0_gpios 6 GPIO_ACTIVE_HIGH>;
enable-active-high;

pinctrl-0 = <&edp_reg_en>;
pinctrl-names = "default";
pinctrl-names = "default";
pinctrl-0 = <&misc_3p3_reg_en>;

regulator-boot-on;
regulator-always-on;
};

vreg_misc_3p3: regulator-misc-3p3 {
vreg_edp_3p3: regulator-edp-3p3 {
compatible = "regulator-fixed";

regulator-name = "VREG_MISC_3P3";
regulator-name = "VREG_EDP_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;

gpio = <&pmh0110_f_e0_gpios 6 GPIO_ACTIVE_HIGH>;
gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
enable-active-high;

pinctrl-names = "default";
pinctrl-0 = <&misc_3p3_reg_en>;
pinctrl-0 = <&edp_reg_en>;
pinctrl-names = "default";

regulator-boot-on;
regulator-always-on;
};

vreg_nvme: regulator-nvme {
Expand Down Expand Up @@ -641,6 +641,12 @@
};
};

&lpass_vamacro {
pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
pinctrl-names = "default";
qcom,dmic-sample-rate = <4800000>;
};

&mdss {
status = "okay";
};
Expand Down Expand Up @@ -682,12 +688,6 @@
status = "okay";
};

&lpass_vamacro {
pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
pinctrl-names = "default";
qcom,dmic-sample-rate = <4800000>;
};

&pcie3b {
vddpe-3v3-supply = <&vreg_nvmesec>;

Expand Down
165 changes: 103 additions & 62 deletions arch/arm64/boot/dts/qcom/glymur.dtsi
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2425,6 +2425,28 @@
status = "disabled";
};

mdss_dp3_phy: phy@faac00 {
compatible = "qcom,glymur-dp-phy";
reg = <0x0 0x00faac00 0x0 0x1d0>,
<0x0 0x00faa400 0x0 0x128>,
<0x0 0x00faa800 0x0 0x128>,
<0x0 0x00faa000 0x0 0x358>;

clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&tcsr TCSR_EDP_CLKREF_EN>;
clock-names = "aux",
"cfg_ahb",
"ref";

power-domains = <&rpmhpd RPMHPD_MX>;

#clock-cells = <1>;
#phy-cells = <0>;

status = "disabled";
};

usb_0_hsphy: phy@fd3000 {
compatible = "qcom,glymur-m31-eusb2-phy",
"qcom,sm8750-m31-eusb2-phy";
Expand Down Expand Up @@ -2571,27 +2593,6 @@
};
};
};
mdss_dp3_phy: phy@faac00 {
compatible = "qcom,glymur-dp-phy";
reg = <0 0x00faac00 0 0x1d0>,
<0 0x00faa400 0 0x128>,
<0 0x00faa800 0 0x128>,
<0 0x00faa000 0 0x358>;

clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&tcsr TCSR_EDP_CLKREF_EN>;
clock-names = "aux",
"cfg_ahb",
"ref";

power-domains = <&rpmhpd RPMHPD_MX>;

#clock-cells = <1>;
#phy-cells = <0>;

status = "disabled";
};

/* cluster0 */
bwmon_cluster0: pmu@100c400 {
Expand Down Expand Up @@ -4825,6 +4826,23 @@
status = "disabled";
};


videocc: clock-controller@0aaf0000 {
compatible = "qcom,glymur-videocc";
reg = <0x0 0x0aaf0000 0x0 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>;

power-domains = <&rpmhpd RPMHPD_MMCX>,
<&rpmhpd RPMHPD_MXC>;
required-opps = <&rpmhpd_opp_low_svs>,
<&rpmhpd_opp_low_svs>;

#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};

mdss: display-subsystem@ae00000 {
compatible = "qcom,glymur-mdss";
reg = <0x0 0x0ae00000 0x0 0x1000>;
Expand Down Expand Up @@ -4860,8 +4878,8 @@

mdss_mdp: display-controller@ae01000 {
compatible = "qcom,glymur-dpu";
reg = <0 0x0ae01000 0 0x93000>,
<0 0x0aeb0000 0 0x2008>;
reg = <0x0 0x0ae01000 0x0 0x93000>,
<0x0 0x0aeb0000 0x0 0x3000>;
reg-names = "mdp",
"vbif";

Expand Down Expand Up @@ -4922,6 +4940,11 @@
mdp_opp_table: opp-table {
compatible = "operating-points-v2";

opp-156000000 {
opp-hz = /bits/ 64 <156000000>;
required-opps = <&rpmhpd_opp_low_svs_d1>;
};

opp-205000000 {
opp-hz = /bits/ 64 <205000000>;
required-opps = <&rpmhpd_opp_low_svs>;
Expand All @@ -4946,16 +4969,30 @@
opp-hz = /bits/ 64 <600000000>;
required-opps = <&rpmhpd_opp_nom_l1>;
};

opp-660000000 {
opp-hz = /bits/ 64 <660000000>;
required-opps = <&rpmhpd_opp_turbo>;
};

opp-717000000 {
opp-hz = /bits/ 64 <717000000>;
required-opps = <&rpmhpd_opp_turbo_l1>;
};
};
};

mdss_dp0: displayport-controller@af54000 {
compatible = "qcom,glymur-dp";
reg = <0x0 0xaf54000 0x0 0x104>,
<0x0 0xaf54200 0x0 0xc0>,
<0x0 0xaf55000 0x0 0x770>,
<0x0 0xaf56000 0x0 0x9c>,
<0x0 0xaf57000 0x0 0x9c>;
reg = <0x0 0xaf54000 0x0 0x200>,
<0x0 0xaf54200 0x0 0x200>,
<0x0 0xaf55000 0x0 0xc00>,
<0x0 0xaf56000 0x0 0x400>,
<0x0 0xaf57000 0x0 0x400>,
<0x0 0xaf58000 0x0 0x400>,
<0x0 0xaf59000 0x0 0x400>,
<0x0 0xaf5a000 0x0 0x600>,
<0x0 0xaf5b000 0x0 0x600>;

interrupts-extended = <&mdss 12>;

Expand All @@ -4969,7 +5006,8 @@
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
"stream_pixel",
"stream_1_pixel";

assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
Expand Down Expand Up @@ -5025,6 +5063,11 @@

opp-540000000 {
opp-hz = /bits/ 64 <540000000>;
required-opps = <&rpmhpd_opp_svs>;
};

opp-675000000 {
opp-hz = /bits/ 64 <675000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};

Expand All @@ -5037,11 +5080,15 @@

mdss_dp1: displayport-controller@af5c000 {
compatible = "qcom,glymur-dp";
reg = <0x0 0xaf5c000 0x0 0x104>,
<0x0 0xaf5c200 0x0 0xc0>,
<0x0 0xaf5d000 0x0 0x770>,
<0x0 0xaf5e000 0x0 0x9c>,
<0x0 0xaf5f000 0x0 0x9c>;
reg = <0x0 0xaf5c000 0x0 0x200>,
<0x0 0xaf5c200 0x0 0x200>,
<0x0 0xaf5d000 0x0 0xc00>,
<0x0 0xaf5e000 0x0 0x400>,
<0x0 0xaf5f000 0x0 0x400>,
<0x0 0xaf60000 0x0 0x400>,
<0x0 0xaf61000 0x0 0x400>,
<0x0 0xaf62000 0x0 0x600>,
<0x0 0xaf63000 0x0 0x600>;

interrupts-extended = <&mdss 13>;

Expand All @@ -5055,7 +5102,8 @@
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
"stream_pixel",
"stream_1_pixel";

assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
Expand Down Expand Up @@ -5099,11 +5147,15 @@

mdss_dp2: displayport-controller@af64000 {
compatible = "qcom,glymur-dp";
reg = <0x0 0x0af64000 0x0 0x104>,
<0x0 0x0af64200 0x0 0xc0>,
<0x0 0x0af65000 0x0 0x770>,
<0x0 0x0af66000 0x0 0x9c>,
<0x0 0x0af67000 0x0 0x9c>;
reg = <0x0 0x0af64000 0x0 0x200>,
<0x0 0x0af64200 0x0 0x200>,
<0x0 0x0af65000 0x0 0xc00>,
<0x0 0x0af66000 0x0 0x400>,
<0x0 0x0af67000 0x0 0x400>,
<0x0 0x0af68000 0x0 0x400>,
<0x0 0x0af69000 0x0 0x400>,
<0x0 0x0af6a000 0x0 0x600>,
<0x0 0x0af6b000 0x0 0x600>;

interrupts-extended = <&mdss 14>;

Expand All @@ -5117,7 +5169,8 @@
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
"stream_pixel",
"stream_1_pixel";

assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
Expand Down Expand Up @@ -5160,11 +5213,15 @@

mdss_dp3: displayport-controller@af6c000 {
compatible = "qcom,glymur-dp";
reg = <0 0x0af6c000 0 0x200>,
<0 0x0af6c200 0 0x200>,
<0 0x0af6d000 0 0xc00>,
<0 0x0af6e000 0 0x400>,
<0 0x0af6f000 0 0x400>;
reg = <0x0 0x0af6c000 0x0 0x200>,
<0x0 0x0af6c200 0x0 0x200>,
<0x0 0x0af6d000 0x0 0xc00>,
<0x0 0x0af6e000 0x0 0x400>,
<0x0 0x0af6f000 0x0 0x400>,
<0x0 0x0af70000 0x0 0x400>,
<0x0 0x0af71000 0x0 0x400>,
<0x0 0x0af72000 0x0 0x600>,
<0x0 0x0af73000 0x0 0x600>;

interrupts-extended = <&mdss 15>;

Expand Down Expand Up @@ -5217,22 +5274,6 @@
};
};

videocc: clock-controller@0aaf0000 {
compatible = "qcom,glymur-videocc";
reg = <0x0 0x0aaf0000 0x0 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>;

power-domains = <&rpmhpd RPMHPD_MMCX>,
<&rpmhpd RPMHPD_MXC>;
required-opps = <&rpmhpd_opp_low_svs>,
<&rpmhpd_opp_low_svs>;

#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};

dispcc: clock-controller@af00000 {
compatible = "qcom,glymur-dispcc";
reg = <0x0 0x0af00000 0x0 0x20000>;
Expand Down