Rg/update cluster peripherals#113
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RiccardoGandolfi wants to merge 12 commits intopulp-platform:masterfrom
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Rg/update cluster peripherals#113RiccardoGandolfi wants to merge 12 commits intopulp-platform:masterfrom
RiccardoGandolfi wants to merge 12 commits intopulp-platform:masterfrom
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…arallel channels, synthesis fixes on backend modules; added rule for mchan/iDMA selection when generating bender scripts; Minor fixes and code cleaning; VCD dumping in testbench. * First changes for latest idma integration into pulp_cluster: updated bender dependencies, Makefile points to fork of regression tests with updated tests, few parameter changes for idma instance * Updated idma_wrap.sv -> added muxing on twod_req for correct selection of the stream channel * Updated Makefile to point to my forks of regression_tests and pulp_runtime * Minor clean-up * Updated idma_wrap: added typedef for passing stream_idx as part of idma_nd_req_t; Updated connections to frontend * Updated Makefile: added updated commits from forks for regression_tests and pulp-runtime * Updated Makefile: updated references to regression tests and pulp-runtime commits * Updated idma_wrap.sv, updated references to regression-tests in Makefile, updated iDMA entry in bender.yml * Updated regression tests commit in Makefile * Changed axi_dw_converter_intf instance to axi_dw_converter * Updated cluster_icache entry in bender.yml * Added QuestaOne option for pulp cluster + removed automatic run-all and add log from start.tcl * Removed wrong working_dir idma reference from Bender.lock * Makefile: Add basic Questa Lint/CDC flows * Updated default pulp cluster configuration in pulp_cluster_package: fixed some synthesis errors on mismatching widths inside iDMA * Added patch for synthesis in Bender.yml + Added synth targs and defs to lint flow * Removed synth targ that was breaking linting compilation * Updated some entries after cluster realignment * Using Chips IT repo for iDMA * Updated Bender.lock with Chips IT iDMA * Added rule to generate iDMA rtl before compiling * Changed idma_wrap for synthesis --> ongoing * Change parameter AXI_ADDR_WIDTH to ADDR_WIDTH in obi-related logic * Add muxing logic on HwpePresent for DW inside HciHwpeSizeParam * Fixed Bender.yml entries + re-added missing synth flag + Fix on idma_wrap in obi typedefs (AXI_ID_WIDTH) * Remapping address for cluster * Add some FIXME and fix some typos * Updated regression-tests and pulp-runtime entries in Makefile (now pointing to chips-it forks); Removed synth targs from linting compile rule; Removed qwavedb option from run option * Added iDMA rtl generation to init rule in Makefile * Updated rules for linting in Makefile * Makefile: Add venv target to ease iDMA rtl generation * Bender.lock: Fix HCI commit * Makefile: Bump regression_test commit and use HTTPS remote * Increased QUEUE_FIFO_DEPTH parameter for iDMA * Added CLUSTER_BASE_ADDR as parameter passed to core_region * Removed base_addr_i signal --> added parameter instead * Removed base_addr_i signal from pulp_cluster_wrap interface * Removed base_addr_i signal from pulp_cluster_tb * Add obi2axi interface to match AXI_ADDR_WIDTH to ADD_WIDTH bus * Fix synthesis issue after removal of base_addr_i signal in periph_data_demux * Removed commented lines in start.tcl script + removed extra space in Bender.yml * Trying to revert indentation changes on idma_wrap * Add gate-level sim support * Add VCD dumping * Updated pulp_cluster_tb: updated ifdefs and iDMA busy signal for vcd dumping * Minor fixes: re-added cluster_fetch_en as default signal to dump vcd with; Added separate rule to generate compile.tcl for mchan target; Removed commented code from idma_wrap
* Due to a mismatch between the testbench and Makefile, the clock timeunit was in us instead of ns
* Fixes for QuestaOne simulation without gui * Updateed README.md with QuestaOne flow * Assiging undriven signals to 0 * Minor udpate on iDMA version --> cleaning some Xs * Added axi_burst_splitter module * Updated iDMA commit --> removed useless registers + remapped registers in pulp-runtime * Revert "Added axi_burst_splitter module" This reverts commit 670057e. * Added Burst_len parameter to iDMA + update Bender entry for iDMA * Updated cluster tb with new value for DMAs burst length parameter * Updated hci commit + updated runtime commit (fix on pi_l2_malloc) + aligned memory sizes to cluster instance in pulp-open * Updated iDMA reference --------- Co-authored-by: RiccardoGandolfi <riccardo.gandolfiu@chips.it>
…nth target for iDMA (#10)
When only DMR is enabled for HMR, a width-mismatch warning occurs for tmr_resynch_req_o, resulting in an error during synthesis with DC. In addition, add an assertion to verify that either DMR or TMR is enabled when HMR is present.
…p-runtime + updated regression tests * [IDMA_CLOCK_GATING] First version of explicit clock gating in idma_wrap.sv * [IDMA_CLOCK_GATING] Fixed clock gating (works also for enqueued mode) * [IDMA_CLOCK_GATING] Updated rtl + updated entry for cluster_peripherals Chips-It fork * [IDMA_CLOCK_GATING] Clean-up on signal names + removed datapath clock gating + updated cluster_peripherals entry * [IDMA CLOCK GATING] Updated dmac_wrap.sv with split clock gating: datapath & frontend * [IDMA CLOCK GATING] Fix for hw-controlled datapath clock gating * [IDMA CLOCK GATING] Moved sw-controlled iDMA clock gating cell from wrap to cluster + clean-up on clock gating logic * [MAKEFILE] Updated commits for regression tests and pulp runtime --> updates for iDMA clock gating * [MAKEFILE][IDMA CLOCK GATING] Updated commits for regression tests and pulp runtime after updating iDMA with clock gating features
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@belanoa Opening the new PR here