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ci: add riscv64 wheel builds to release workflow#2139

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abetlen merged 3 commits intoabetlen:mainfrom
gounthar:add-riscv64-wheels
Mar 23, 2026
Merged

ci: add riscv64 wheel builds to release workflow#2139
abetlen merged 3 commits intoabetlen:mainfrom
gounthar:add-riscv64-wheels

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@gounthar
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@gounthar gounthar commented Mar 12, 2026

Summary

Add linux_riscv64 wheels to the release workflow, mirroring the existing
arm64 QEMU-based build job.

Changes

  • New build_wheels_riscv64 job using cibuildwheel + QEMU emulation
  • Targets CPython 3.10–3.14 on manylinux_riscv64
  • Skips musllinux (no riscv64 musllinux image available)
  • Added to the release job dependency list

Evidence

A tested riscv64 wheel is available in our community index:
https://gounthar.github.io/riscv64-python-wheels/simple/llama-cpp-python/

Built natively on BananaPi F3 (SpacemiT K1, rv64imafdcv, 8 cores @ 1.6 GHz, 16 GB RAM).

Context

  • manylinux_2_28_riscv64 is available in pypa/manylinux
  • cibuildwheel supports riscv64 via QEMU
  • Several packages already ship riscv64 wheels on PyPI (aiohttp, yarl, multidict, regex, charset-normalizer)
  • RISC-V hardware is shipping (SiFive, SpacemiT K1/K3, Sophgo SG2044)

Closes #2138


Note: this work is part of the RISE Project effort to improve Python ecosystem support on riscv64 platforms. Native riscv64 CI runners are available for free via RISE RISC-V runners.

@gounthar
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Native build verified on riscv64 hardware (BananaPi F3, SpacemiT K1, rv64gc, GCC 14.2.0): SUCCESS.

gounthar and others added 3 commits March 22, 2026 19:22
Add a build_wheels_riscv64 job mirroring the existing arm64 QEMU-based
build. Uses cibuildwheel with QEMU emulation for linux/riscv64, targeting
CPython 3.10-3.14 on manylinux.

Closes abetlen#2138
@abetlen abetlen force-pushed the add-riscv64-wheels branch from abb0a24 to 7bb6d6b Compare March 23, 2026 02:23
@abetlen
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abetlen commented Mar 23, 2026

Thank you @gounthar this should be in the next release.

note: I updated the cibuildwheel version because codex tells me the option only appears >3.x

@abetlen abetlen merged commit e1f8ac0 into abetlen:main Mar 23, 2026
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@gounthar
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Thanks for merging this.

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Add riscv64 (linux_riscv64) wheel to PyPI releases

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