From 53cdefa7256b735144bac56eb6ffe3483c5db79d Mon Sep 17 00:00:00 2001 From: kas User Date: Tue, 10 Mar 2026 12:55:10 +0530 Subject: [PATCH 1/4] Revert "PENDING: arm64: dts: qcom: glymur: Describe display related nodes" This reverts commit 121d0653db2583fafb2c8a16e5cf89d84006de2a. Signed-off-by: Nabige Aala --- arch/arm64/boot/dts/qcom/glymur.dtsi | 431 +-------------------------- 1 file changed, 8 insertions(+), 423 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 48adc83c9aff7..38fa96f51606b 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -2492,7 +2492,6 @@ reg = <2>; usb_dp_qmpphy_dp_in: endpoint { - remote-endpoint = <&mdss_dp0_out>; }; }; }; @@ -2566,32 +2565,10 @@ reg = <2>; usb_1_qmpphy_dp_in: endpoint { - remote-endpoint = <&mdss_dp1_out>; }; }; }; }; - mdss_dp3_phy: phy@faac00 { - compatible = "qcom,glymur-dp-phy"; - reg = <0 0x00faac00 0 0x1d0>, - <0 0x00faa400 0 0x128>, - <0 0x00faa800 0 0x128>, - <0 0x00faa000 0 0x358>; - - clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&tcsr TCSR_EDP_CLKREF_EN>; - clock-names = "aux", - "cfg_ahb", - "ref"; - - power-domains = <&rpmhpd RPMHPD_MX>; - - #clock-cells = <1>; - #phy-cells = <0>; - - status = "disabled"; - }; /* cluster0 */ bwmon_cluster0: pmu@100c400 { @@ -4460,7 +4437,6 @@ reg = <2>; usb_2_qmpphy_dp_in: endpoint { - remote-endpoint = <&mdss_dp2_out>; }; }; }; @@ -4825,397 +4801,6 @@ status = "disabled"; }; - mdss: display-subsystem@ae00000 { - compatible = "qcom,glymur-mdss"; - reg = <0x0 0x0ae00000 0x0 0x1000>; - reg-names = "mdss"; - - interrupts = ; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>; - - resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; - - interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "mdp0-mem", - "cpu-cfg"; - - power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; - - iommus = <&apps_smmu 0x1de0 0x2>; - - interrupt-controller; - #interrupt-cells = <1>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - status = "disabled"; - - mdss_mdp: display-controller@ae01000 { - compatible = "qcom,glymur-dpu"; - reg = <0 0x0ae01000 0 0x93000>, - <0 0x0aeb0000 0 0x2008>; - reg-names = "mdp", - "vbif"; - - interrupts-extended = <&mdss 0>; - - clocks = <&gcc GCC_DISP_HF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "nrt_bus", - "iface", - "lut", - "core", - "vsync"; - - operating-points-v2 = <&mdp_opp_table>; - - power-domains = <&rpmhpd RPMHPD_MMCX>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dpu_intf0_out: endpoint { - remote-endpoint = <&mdss_dp0_in>; - }; - }; - - port@4 { - reg = <4>; - - mdss_intf4_out: endpoint { - remote-endpoint = <&mdss_dp1_in>; - }; - }; - - port@5 { - reg = <5>; - - mdss_intf5_out: endpoint { - remote-endpoint = <&mdss_dp3_in>; - }; - }; - - port@6 { - reg = <6>; - - mdss_intf6_out: endpoint { - remote-endpoint = <&mdss_dp2_in>; - }; - }; - }; - - mdp_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-205000000 { - opp-hz = /bits/ 64 <205000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-337000000 { - opp-hz = /bits/ 64 <337000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-417000000 { - opp-hz = /bits/ 64 <417000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-532000000 { - opp-hz = /bits/ 64 <532000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - required-opps = <&rpmhpd_opp_nom_l1>; - }; - }; - }; - - mdss_dp0: displayport-controller@af54000 { - compatible = "qcom,glymur-dp"; - reg = <0x0 0xaf54000 0x0 0x104>, - <0x0 0xaf54200 0x0 0xc0>, - <0x0 0xaf55000 0x0 0x770>, - <0x0 0xaf56000 0x0 0x9c>, - <0x0 0xaf57000 0x0 0x9c>; - - interrupts-extended = <&mdss 12>; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, - <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, - <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; - clock-names = "core_iface", - "core_aux", - "ctrl_link", - "ctrl_link_iface", - "stream_pixel"; - - assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; - assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, - <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, - <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; - - operating-points-v2 = <&mdss_dp0_opp_table>; - - power-domains = <&rpmhpd RPMHPD_MMCX>; - - phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; - phy-names = "dp"; - - #sound-dai-cells = <0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mdss_dp0_in: endpoint { - remote-endpoint = <&dpu_intf0_out>; - }; - }; - - port@1 { - reg = <1>; - - mdss_dp0_out: endpoint { - remote-endpoint = <&usb_dp_qmpphy_dp_in>; - }; - }; - }; - - mdss_dp0_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-192000000 { - opp-hz = /bits/ 64 <192000000>; - required-opps = <&rpmhpd_opp_low_svs_d1>; - }; - - opp-270000000 { - opp-hz = /bits/ 64 <270000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-540000000 { - opp-hz = /bits/ 64 <540000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-810000000 { - opp-hz = /bits/ 64 <810000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - }; - - mdss_dp1: displayport-controller@af5c000 { - compatible = "qcom,glymur-dp"; - reg = <0x0 0xaf5c000 0x0 0x104>, - <0x0 0xaf5c200 0x0 0xc0>, - <0x0 0xaf5d000 0x0 0x770>, - <0x0 0xaf5e000 0x0 0x9c>, - <0x0 0xaf5f000 0x0 0x9c>; - - interrupts-extended = <&mdss 13>; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, - <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, - <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, - <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; - clock-names = "core_iface", - "core_aux", - "ctrl_link", - "ctrl_link_iface", - "stream_pixel"; - - assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; - assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, - <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, - <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; - - operating-points-v2 = <&mdss_dp0_opp_table>; - - power-domains = <&rpmhpd RPMHPD_MMCX>; - - phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; - phy-names = "dp"; - - #sound-dai-cells = <0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mdss_dp1_in: endpoint { - remote-endpoint = <&mdss_intf4_out>; - }; - }; - - port@1 { - reg = <1>; - - mdss_dp1_out: endpoint { - remote-endpoint = <&usb_1_qmpphy_dp_in>; - }; - }; - }; - }; - - mdss_dp2: displayport-controller@af64000 { - compatible = "qcom,glymur-dp"; - reg = <0x0 0x0af64000 0x0 0x104>, - <0x0 0x0af64200 0x0 0xc0>, - <0x0 0x0af65000 0x0 0x770>, - <0x0 0x0af66000 0x0 0x9c>, - <0x0 0x0af67000 0x0 0x9c>; - - interrupts-extended = <&mdss 14>; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, - <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, - <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, - <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; - clock-names = "core_iface", - "core_aux", - "ctrl_link", - "ctrl_link_iface", - "stream_pixel"; - - assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; - assigned-clock-parents = <&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>, - <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, - <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; - - operating-points-v2 = <&mdss_dp0_opp_table>; - - power-domains = <&rpmhpd RPMHPD_MMCX>; - - phys = <&usb_2_qmpphy QMP_USB43DP_DP_PHY>; - phy-names = "dp"; - - #sound-dai-cells = <0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mdss_dp2_in: endpoint { - remote-endpoint = <&mdss_intf6_out>; - }; - }; - - port@1 { - reg = <1>; - - mdss_dp2_out: endpoint { - remote-endpoint = <&usb_2_qmpphy_dp_in>; - }; - }; - }; - }; - - mdss_dp3: displayport-controller@af6c000 { - compatible = "qcom,glymur-dp"; - reg = <0 0x0af6c000 0 0x200>, - <0 0x0af6c200 0 0x200>, - <0 0x0af6d000 0 0xc00>, - <0 0x0af6e000 0 0x400>, - <0 0x0af6f000 0 0x400>; - - interrupts-extended = <&mdss 15>; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, - <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, - <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; - clock-names = "core_iface", - "core_aux", - "ctrl_link", - "ctrl_link_iface", - "stream_pixel"; - - assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; - assigned-clock-parents = <&mdss_dp3_phy 0>, - <&mdss_dp3_phy 1>; - - operating-points-v2 = <&mdss_dp0_opp_table>; - - power-domains = <&rpmhpd RPMHPD_MMCX>; - - phys = <&mdss_dp3_phy>; - phy-names = "dp"; - - #sound-dai-cells = <0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mdss_dp3_in: endpoint { - remote-endpoint = <&mdss_intf5_out>; - }; - }; - - port@1 { - reg = <1>; - - mdss_dp3_out: endpoint { - }; - }; - }; - }; - }; videocc: clock-controller@0aaf0000 { compatible = "qcom,glymur-videocc"; @@ -5238,14 +4823,14 @@ reg = <0x0 0x0af00000 0x0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, - <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ - <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, - <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ - <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, - <&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ - <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, - <&mdss_dp3_phy 0>, /* dp3 */ - <&mdss_dp3_phy 1>, + <0>, /* dp0 */ + <0>, + <0>, /* dp1 */ + <0>, + <0>, /* dp2 */ + <0>, + <0>, /* dp3 */ + <0>, <0>, /* dsi0 */ <0>, <0>, /* dsi1 */ From 4590030713e29e66539f5b8fcf377f153d99d0cb Mon Sep 17 00:00:00 2001 From: Nabige Aala Date: Mon, 9 Mar 2026 14:41:02 +0530 Subject: [PATCH 2/4] Revert "PENDING: arm64: dts: qcom: glymur-crd: Enable eDP display" This reverts commit 94979b974437639ee5e0ddfbad0f97908bd3d701. Signed-off-by: Nabige Aala --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 71 ------------------------- 1 file changed, 71 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index 6ceaa44028790..ecfbacf74c03f 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -153,22 +153,6 @@ }; }; - vreg_edp_3p3: regulator-edp-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_EDP_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&edp_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - vreg_misc_3p3: regulator-misc-3p3 { compatible = "regulator-fixed"; @@ -641,47 +625,6 @@ }; }; -&mdss { - status = "okay"; -}; - -&mdss_dp3 { - /delete-property/ #sound-dai-cells; - - status = "okay"; - - aux-bus { - panel { - compatible = "samsung,atna60cl08", "samsung,atna33xc20"; - enable-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; - power-supply = <&vreg_edp_3p3>; - - pinctrl-0 = <&edp_bl_en>; - pinctrl-names = "default"; - - port { - edp_panel_in: endpoint { - remote-endpoint = <&mdss_dp3_out>; - }; - }; - }; - }; -}; - -&mdss_dp3_out { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - - remote-endpoint = <&edp_panel_in>; -}; - -&mdss_dp3_phy { - vdda-phy-supply = <&vreg_l2f_e1_0p83>; - vdda-pll-supply = <&vreg_l4f_e1_1p08>; - - status = "okay"; -}; - &lpass_vamacro { pinctrl-0 = <&dmic01_default>, <&dmic23_default>; pinctrl-names = "default"; @@ -925,20 +868,6 @@ <10 2>, /* OOB UART */ <44 4>; /* Security SPI (TPM) */ - edp_bl_en: edp-bl-en-state { - pins = "gpio18"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - - edp_reg_en: edp-reg-en-state { - pins = "gpio70"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - pcie4_default: pcie4-default-state { clkreq-n-pins { pins = "gpio147"; From a239838b7394666715d042c0ad8694676919d16b Mon Sep 17 00:00:00 2001 From: Nabige Aala Date: Mon, 9 Mar 2026 14:59:41 +0530 Subject: [PATCH 3/4] FROMLIST: arm64: dts: qcom: glymur: Describe display related nodes The MDSS (Mobile Display SubSystem) on Glymur comes with 4 DisplayPort controllers. Describe them along with display controller and the eDP PHY. Then, attach the combo PHYs link and vco_div clocks to the Display clock controller and link up the PHYs and DP endpoints in the graph. Link: https://lore.kernel.org/all/20260303-dts-qcom-glymur-crd-add-edp-v3-1-4d1ffcb1d9f6@oss.qualcomm.com/ Signed-off-by: Abel Vesa Signed-off-by: Abel Vesa Signed-off-by: Nabige Aala --- arch/arm64/boot/dts/qcom/glymur.dtsi | 472 ++++++++++++++++++++++++++- 1 file changed, 464 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 38fa96f51606b..7e4bc3220d998 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -2425,6 +2425,28 @@ status = "disabled"; }; + mdss_dp3_phy: phy@faac00 { + compatible = "qcom,glymur-dp-phy"; + reg = <0x0 0x00faac00 0x0 0x1d0>, + <0x0 0x00faa400 0x0 0x128>, + <0x0 0x00faa800 0x0 0x128>, + <0x0 0x00faa000 0x0 0x358>; + + clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&tcsr TCSR_EDP_CLKREF_EN>; + clock-names = "aux", + "cfg_ahb", + "ref"; + + power-domains = <&rpmhpd RPMHPD_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + usb_0_hsphy: phy@fd3000 { compatible = "qcom,glymur-m31-eusb2-phy", "qcom,sm8750-m31-eusb2-phy"; @@ -2492,6 +2514,7 @@ reg = <2>; usb_dp_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; }; }; }; @@ -2565,6 +2588,7 @@ reg = <2>; usb_1_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp1_out>; }; }; }; @@ -4437,6 +4461,7 @@ reg = <2>; usb_2_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp2_out>; }; }; }; @@ -4818,19 +4843,450 @@ #power-domain-cells = <1>; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,glymur-mdss"; + reg = <0x0 0x0ae00000 0x0 0x1000>; + reg-names = "mdss"; + + interrupts = ; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + + iommus = <&apps_smmu 0x1de0 0x2>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,glymur-dpu"; + reg = <0x0 0x0ae01000 0x0 0x93000>, + <0x0 0x0aeb0000 0x0 0x3000>; + reg-names = "mdp", + "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; + + port@4 { + reg = <4>; + + mdss_intf4_out: endpoint { + remote-endpoint = <&mdss_dp1_in>; + }; + }; + + port@5 { + reg = <5>; + + mdss_intf5_out: endpoint { + remote-endpoint = <&mdss_dp3_in>; + }; + }; + + port@6 { + reg = <6>; + + mdss_intf6_out: endpoint { + remote-endpoint = <&mdss_dp2_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-156000000 { + opp-hz = /bits/ 64 <156000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-205000000 { + opp-hz = /bits/ 64 <205000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-337000000 { + opp-hz = /bits/ 64 <337000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz = /bits/ 64 <417000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz = /bits/ 64 <532000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + + opp-660000000 { + opp-hz = /bits/ 64 <660000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + + opp-717000000 { + opp-hz = /bits/ 64 <717000000>; + required-opps = <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + + mdss_dp0: displayport-controller@af54000 { + compatible = "qcom,glymur-dp"; + reg = <0x0 0xaf54000 0x0 0x200>, + <0x0 0xaf54200 0x0 0x200>, + <0x0 0xaf55000 0x0 0xc00>, + <0x0 0xaf56000 0x0 0x400>, + <0x0 0xaf57000 0x0 0x400>, + <0x0 0xaf58000 0x0 0x400>, + <0x0 0xaf59000 0x0 0x400>, + <0x0 0xaf5a000 0x0 0x600>, + <0x0 0xaf5b000 0x0 0x600>; + + interrupts-extended = <&mdss 12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + remote-endpoint = <&usb_dp_qmpphy_dp_in>; + }; + }; + }; + + mdss_dp0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-675000000 { + opp-hz = /bits/ 64 <675000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dp1: displayport-controller@af5c000 { + compatible = "qcom,glymur-dp"; + reg = <0x0 0xaf5c000 0x0 0x200>, + <0x0 0xaf5c200 0x0 0x200>, + <0x0 0xaf5d000 0x0 0xc00>, + <0x0 0xaf5e000 0x0 0x400>, + <0x0 0xaf5f000 0x0 0x400>, + <0x0 0xaf60000 0x0 0x400>, + <0x0 0xaf61000 0x0 0x400>, + <0x0 0xaf62000 0x0 0x600>, + <0x0 0xaf63000 0x0 0x600>; + + interrupts-extended = <&mdss 13>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp1_in: endpoint { + remote-endpoint = <&mdss_intf4_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp1_out: endpoint { + remote-endpoint = <&usb_1_qmpphy_dp_in>; + }; + }; + }; + }; + + mdss_dp2: displayport-controller@af64000 { + compatible = "qcom,glymur-dp"; + reg = <0x0 0x0af64000 0x0 0x200>, + <0x0 0x0af64200 0x0 0x200>, + <0x0 0x0af65000 0x0 0xc00>, + <0x0 0x0af66000 0x0 0x400>, + <0x0 0x0af67000 0x0 0x400>, + <0x0 0x0af68000 0x0 0x400>, + <0x0 0x0af69000 0x0 0x400>, + <0x0 0x0af6a000 0x0 0x600>, + <0x0 0x0af6b000 0x0 0x600>; + + interrupts-extended = <&mdss 14>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_2_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dp2_in: endpoint { + remote-endpoint = <&mdss_intf6_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp2_out: endpoint { + remote-endpoint = <&usb_2_qmpphy_dp_in>; + }; + }; + }; + }; + + mdss_dp3: displayport-controller@af6c000 { + compatible = "qcom,glymur-dp"; + reg = <0x0 0x0af6c000 0x0 0x200>, + <0x0 0x0af6c200 0x0 0x200>, + <0x0 0x0af6d000 0x0 0xc00>, + <0x0 0x0af6e000 0x0 0x400>, + <0x0 0x0af6f000 0x0 0x400>, + <0x0 0x0af70000 0x0 0x400>, + <0x0 0x0af71000 0x0 0x400>, + <0x0 0x0af72000 0x0 0x600>, + <0x0 0x0af73000 0x0 0x600>; + + interrupts-extended = <&mdss 15>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss_dp3_phy 0>, + <&mdss_dp3_phy 1>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dp3_phy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp3_in: endpoint { + remote-endpoint = <&mdss_intf5_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp3_out: endpoint { + }; + }; + }; + }; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,glymur-dispcc"; reg = <0x0 0x0af00000 0x0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, - <0>, /* dp0 */ - <0>, - <0>, /* dp1 */ - <0>, - <0>, /* dp2 */ - <0>, - <0>, /* dp3 */ - <0>, + <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ + <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ + <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&mdss_dp3_phy 0>, /* dp3 */ + <&mdss_dp3_phy 1>, <0>, /* dsi0 */ <0>, <0>, /* dsi1 */ From 2b16cc0f2da26a2983a050a2189e3490eff6deb6 Mon Sep 17 00:00:00 2001 From: Nabige Aala Date: Mon, 9 Mar 2026 15:03:52 +0530 Subject: [PATCH 4/4] FROMLIST: arm64: dts: qcom: glymur-crd: Enable eDP display support Enable the MDSS (Mobile Display SubSystem) along with the 3rd DisplayPort controller and its PHY in order to bring support for the panel on Glymur CRD platform. Also describe the voltage regulator needed by the eDP panel. Link: https://lore.kernel.org/all/20260303-dts-qcom-glymur-crd-add-edp-v3-2-4d1ffcb1d9f6@oss.qualcomm.com/ Signed-off-by: Abel Vesa Signed-off-by: Abel Vesa Signed-off-by: Nabige Aala --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 71 +++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index ecfbacf74c03f..62459d5bd2f38 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -170,6 +170,22 @@ regulator-always-on; }; + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + vreg_nvme: regulator-nvme { compatible = "regulator-fixed"; @@ -631,6 +647,47 @@ qcom,dmic-sample-rate = <4800000>; }; +&mdss { + status = "okay"; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + status = "okay"; + + aux-bus { + panel { + compatible = "samsung,atna60cl08", "samsung,atna33xc20"; + enable-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_3p3>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l2f_e1_0p83>; + vdda-pll-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; + &pcie3b { vddpe-3v3-supply = <&vreg_nvmesec>; @@ -868,6 +925,20 @@ <10 2>, /* OOB UART */ <44 4>; /* Security SPI (TPM) */ + edp_bl_en: edp-bl-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + pcie4_default: pcie4-default-state { clkreq-n-pins { pins = "gpio147";