diff --git a/ADL/events/alderlake_goldencove_core.json b/ADL/events/alderlake_goldencove_core.json index 3b4bde02..4b8b375a 100644 --- a/ADL/events/alderlake_goldencove_core.json +++ b/ADL/events/alderlake_goldencove_core.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.36", - "DatePublished": "11/17/2025", - "Version": "1.36", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.37", + "DatePublished": "01/13/2026", + "Version": "1.37", "Legend": "" }, "Events": [ diff --git a/ADL/events/alderlake_gracemont_core.json b/ADL/events/alderlake_gracemont_core.json index 7cfefad5..6585bd5d 100644 --- a/ADL/events/alderlake_gracemont_core.json +++ b/ADL/events/alderlake_gracemont_core.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.36", - "DatePublished": "11/17/2025", - "Version": "1.36", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.37", + "DatePublished": "01/13/2026", + "Version": "1.37", "Legend": "" }, "Events": [ @@ -11,7 +11,7 @@ "EventCode": "0x00", "UMask": "0x01", "EventName": "INST_RETIRED.ANY", - "BriefDescription": "Counts the total number of instructions retired. (Fixed event)", + "BriefDescription": "Fixed Counter: Counts the total number of instructions retired.", "PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0.", "Counter": "Fixed counter 0", "PEBScounters": "32", @@ -36,7 +36,7 @@ "EventCode": "0x00", "UMask": "0x02", "EventName": "CPU_CLK_UNHALTED.CORE", - "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)", + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]", "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.", "Counter": "Fixed counter 1", "PEBScounters": "33", @@ -86,7 +86,7 @@ "EventCode": "0x00", "UMask": "0x03", "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)", + "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles at TSC frequency.", "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.", "Counter": "Fixed counter 2", "PEBScounters": "34", @@ -836,7 +836,7 @@ "EventCode": "0x3c", "UMask": "0x00", "EventName": "CPU_CLK_UNHALTED.CORE_P", - "BriefDescription": "Counts the number of unhalted core clock cycles.", + "BriefDescription": "Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD_P]", "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.", "Counter": "0,1,2,3,4,5", "PEBScounters": "0,1,2,3,4,5", diff --git a/ADL/events/alderlake_uncore.json b/ADL/events/alderlake_uncore.json index 2bf7db3b..6b520aaf 100644 --- a/ADL/events/alderlake_uncore.json +++ b/ADL/events/alderlake_uncore.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.36", - "DatePublished": "11/17/2025", - "Version": "1.36", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.37", + "DatePublished": "01/13/2026", + "Version": "1.37", "Legend": "" }, "Events": [ diff --git a/ADL/events/alderlake_uncore_experimental.json b/ADL/events/alderlake_uncore_experimental.json index 0cc62d72..cffb695f 100644 --- a/ADL/events/alderlake_uncore_experimental.json +++ b/ADL/events/alderlake_uncore_experimental.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.36", - "DatePublished": "11/17/2025", - "Version": "1.36", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.37", + "DatePublished": "01/13/2026", + "Version": "1.37", "Legend": "" }, "Events": [ diff --git a/ARL/events/arrowlake_crestmont_core.json b/ARL/events/arrowlake_crestmont_core.json index 400305ae..fa18d9d7 100644 --- a/ARL/events/arrowlake_crestmont_core.json +++ b/ARL/events/arrowlake_crestmont_core.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.15", - "DatePublished": "11/20/2025", - "Version": "1.15", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.16", + "DatePublished": "01/13/2026", + "Version": "1.16", "Legend": "" }, "Events": [ @@ -12,8 +12,8 @@ "UMask": "0x01", "UMaskExt": "0x00", "EventName": "INST_RETIRED.ANY", - "BriefDescription": "Fixed Counter: Counts the number of instructions retired", - "PublicDescription": "Fixed Counter: Counts the number of instructions retired", + "BriefDescription": "Fixed Counter: Counts the number of instructions retired.", + "PublicDescription": "Fixed Counter: Counts the number of instructions retired.", "Counter": "Fixed counter 0", "PEBScounters": "32", "SampleAfterValue": "2000003", @@ -39,8 +39,8 @@ "UMask": "0x02", "UMaskExt": "0x00", "EventName": "CPU_CLK_UNHALTED.CORE", - "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", - "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]", + "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]", "Counter": "Fixed counter 1", "PEBScounters": "33", "SampleAfterValue": "2000003", @@ -93,8 +93,8 @@ "UMask": "0x03", "UMaskExt": "0x00", "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles", - "PublicDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles", + "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles.", + "PublicDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles.", "Counter": "Fixed counter 2", "PEBScounters": "34", "SampleAfterValue": "2000003", diff --git a/ARL/events/arrowlake_lioncove_core.json b/ARL/events/arrowlake_lioncove_core.json index fbd6aed2..fbf5c779 100644 --- a/ARL/events/arrowlake_lioncove_core.json +++ b/ARL/events/arrowlake_lioncove_core.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.15", - "DatePublished": "11/20/2025", - "Version": "1.15", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.16", + "DatePublished": "01/13/2026", + "Version": "1.16", "Legend": "" }, "Events": [ diff --git a/ARL/events/arrowlake_skymont_core.json b/ARL/events/arrowlake_skymont_core.json index ba03111c..995dc668 100644 --- a/ARL/events/arrowlake_skymont_core.json +++ b/ARL/events/arrowlake_skymont_core.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.15", - "DatePublished": "11/20/2025", - "Version": "1.15", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.16", + "DatePublished": "01/13/2026", + "Version": "1.16", "Legend": "" }, "Events": [ @@ -39,8 +39,8 @@ "UMask": "0x02", "UMaskExt": "0x00", "EventName": "CPU_CLK_UNHALTED.CORE", - "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles.", - "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles.", + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]", + "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]", "Counter": "Fixed counter 1", "PEBScounters": "33", "SampleAfterValue": "2000003", diff --git a/ARL/events/arrowlake_uncore.json b/ARL/events/arrowlake_uncore.json index 25f8e716..4efdfaba 100644 --- a/ARL/events/arrowlake_uncore.json +++ b/ARL/events/arrowlake_uncore.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.15", - "DatePublished": "11/20/2025", - "Version": "1.15", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.16", + "DatePublished": "01/13/2026", + "Version": "1.16", "Legend": "" }, "Events": [ diff --git a/ARL/events/arrowlake_uncore_experimental.json b/ARL/events/arrowlake_uncore_experimental.json index 0ddaf7cf..f092e46a 100644 --- a/ARL/events/arrowlake_uncore_experimental.json +++ b/ARL/events/arrowlake_uncore_experimental.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.15", - "DatePublished": "11/20/2025", - "Version": "1.15", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.16", + "DatePublished": "01/13/2026", + "Version": "1.16", "Legend": "" }, "Events": [ diff --git a/GRR/events/grandridge_core.json b/GRR/events/grandridge_core.json index 70cd77ad..6ca5e3a7 100644 --- a/GRR/events/grandridge_core.json +++ b/GRR/events/grandridge_core.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Grand Ridge Base Transceiver Station Family - V1.10", - "DatePublished": "08/28/2025", - "Version": "1.10", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Grand Ridge Base Transceiver Station Family - V1.11", + "DatePublished": "01/13/2026", + "Version": "1.11", "Legend": "" }, "Events": [ @@ -11,8 +11,8 @@ "EventCode": "0x00", "UMask": "0x01", "EventName": "INST_RETIRED.ANY", - "BriefDescription": "Fixed Counter: Counts the number of instructions retired", - "PublicDescription": "Fixed Counter: Counts the number of instructions retired", + "BriefDescription": "Fixed Counter: Counts the number of instructions retired.", + "PublicDescription": "Fixed Counter: Counts the number of instructions retired.", "Counter": "Fixed counter 0", "PEBScounters": "32", "SampleAfterValue": "2000003", @@ -36,8 +36,8 @@ "EventCode": "0x00", "UMask": "0x02", "EventName": "CPU_CLK_UNHALTED.CORE", - "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", - "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]", + "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]", "Counter": "Fixed counter 1", "PEBScounters": "33", "SampleAfterValue": "2000003", @@ -61,8 +61,8 @@ "EventCode": "0x00", "UMask": "0x02", "EventName": "CPU_CLK_UNHALTED.THREAD", - "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", - "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]", + "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]", "Counter": "Fixed counter 1", "PEBScounters": "33", "SampleAfterValue": "2000003", @@ -86,8 +86,8 @@ "EventCode": "0x00", "UMask": "0x03", "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles", - "PublicDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles", + "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles.", + "PublicDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles.", "Counter": "Fixed counter 2", "PEBScounters": "34", "SampleAfterValue": "2000003", @@ -3439,12 +3439,12 @@ "BriefDescription": "Counts the number of cycles when any of the floating point dividers are active.", "PublicDescription": "Counts the number of cycles when any of the floating point dividers are active.", "Counter": "0,1,2,3,4,5,6,7", - "PEBScounters": "NA", + "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", - "CollectPEBSRecord": "0", + "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "1", "Invert": "0", @@ -3464,12 +3464,12 @@ "BriefDescription": "Counts the number of cycles when any of the floating point or integer dividers are active.", "PublicDescription": "Counts the number of cycles when any of the floating point or integer dividers are active.", "Counter": "0,1,2,3,4,5,6,7", - "PEBScounters": "NA", + "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", - "CollectPEBSRecord": "0", + "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "1", "Invert": "0", @@ -3486,15 +3486,15 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "Counter": "0,1,2,3,4,5,6,7", - "PEBScounters": "0,1,2,3,4,5,6,7", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8. Only counts with PEBS enabled.", + "Counter": "0,1", + "PEBScounters": "0,1", "SampleAfterValue": "1000003", "MSRIndex": "0x3F6", "MSRValue": "0x8", "Precise": "1", - "CollectPEBSRecord": "2", + "CollectPEBSRecord": "3", "TakenAlone": "1", "CounterMask": "0", "Invert": "0", @@ -3511,15 +3511,15 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "Counter": "0,1,2,3,4,5,6,7", - "PEBScounters": "0,1,2,3,4,5,6,7", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64. Only counts with PEBS enabled.", + "Counter": "0,1", + "PEBScounters": "0,1", "SampleAfterValue": "1000003", "MSRIndex": "0x3F6", "MSRValue": "0x40", "Precise": "1", - "CollectPEBSRecord": "2", + "CollectPEBSRecord": "3", "TakenAlone": "1", "CounterMask": "0", "Invert": "0", @@ -3536,15 +3536,15 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "Counter": "0,1,2,3,4,5,6,7", - "PEBScounters": "0,1,2,3,4,5,6,7", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512. Only counts with PEBS enabled.", + "Counter": "0,1", + "PEBScounters": "0,1", "SampleAfterValue": "1000003", "MSRIndex": "0x3F6", "MSRValue": "0x200", "Precise": "1", - "CollectPEBSRecord": "2", + "CollectPEBSRecord": "3", "TakenAlone": "1", "CounterMask": "0", "Invert": "0", @@ -3561,15 +3561,15 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "Counter": "0,1,2,3,4,5,6,7", - "PEBScounters": "0,1,2,3,4,5,6,7", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4. Only counts with PEBS enabled.", + "Counter": "0,1", + "PEBScounters": "0,1", "SampleAfterValue": "1000003", "MSRIndex": "0x3F6", "MSRValue": "0x4", "Precise": "1", - "CollectPEBSRecord": "2", + "CollectPEBSRecord": "3", "TakenAlone": "1", "CounterMask": "0", "Invert": "0", @@ -3586,15 +3586,15 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "Counter": "0,1,2,3,4,5,6,7", - "PEBScounters": "0,1,2,3,4,5,6,7", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32. Only counts with PEBS enabled.", + "Counter": "0,1", + "PEBScounters": "0,1", "SampleAfterValue": "1000003", "MSRIndex": "0x3F6", "MSRValue": "0x20", "Precise": "1", - "CollectPEBSRecord": "2", + "CollectPEBSRecord": "3", "TakenAlone": "1", "CounterMask": "0", "Invert": "0", @@ -3611,15 +3611,15 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "Counter": "0,1,2,3,4,5,6,7", - "PEBScounters": "0,1,2,3,4,5,6,7", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256. Only counts with PEBS enabled.", + "Counter": "0,1", + "PEBScounters": "0,1", "SampleAfterValue": "1000003", "MSRIndex": "0x3F6", "MSRValue": "0x100", "Precise": "1", - "CollectPEBSRecord": "2", + "CollectPEBSRecord": "3", "TakenAlone": "1", "CounterMask": "0", "Invert": "0", @@ -3636,15 +3636,15 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "Counter": "0,1,2,3,4,5,6,7", - "PEBScounters": "0,1,2,3,4,5,6,7", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16. Only counts with PEBS enabled.", + "Counter": "0,1", + "PEBScounters": "0,1", "SampleAfterValue": "1000003", "MSRIndex": "0x3F6", "MSRValue": "0x10", "Precise": "1", - "CollectPEBSRecord": "2", + "CollectPEBSRecord": "3", "TakenAlone": "1", "CounterMask": "0", "Invert": "0", @@ -3661,15 +3661,15 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "Counter": "0,1,2,3,4,5,6,7", - "PEBScounters": "0,1,2,3,4,5,6,7", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128. Only counts with PEBS enabled.", + "Counter": "0,1", + "PEBScounters": "0,1", "SampleAfterValue": "1000003", "MSRIndex": "0x3F6", "MSRValue": "0x80", "Precise": "1", - "CollectPEBSRecord": "2", + "CollectPEBSRecord": "3", "TakenAlone": "1", "CounterMask": "0", "Invert": "0", @@ -3686,15 +3686,15 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "Counter": "0,1,2,3,4,5,6,7", - "PEBScounters": "0,1,2,3,4,5,6,7", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 2048. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 2048. Only counts with PEBS enabled.", + "Counter": "0,1", + "PEBScounters": "0,1", "SampleAfterValue": "1000003", "MSRIndex": "0x3F6", "MSRValue": "0x800", "Precise": "1", - "CollectPEBSRecord": "2", + "CollectPEBSRecord": "3", "TakenAlone": "1", "CounterMask": "0", "Invert": "0", @@ -3711,15 +3711,15 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "Counter": "0,1,2,3,4,5,6,7", - "PEBScounters": "0,1,2,3,4,5,6,7", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 1024. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 1024. Only counts with PEBS enabled.", + "Counter": "0,1", + "PEBScounters": "0,1", "SampleAfterValue": "1000003", "MSRIndex": "0x3F6", "MSRValue": "0x400", "Precise": "1", - "CollectPEBSRecord": "2", + "CollectPEBSRecord": "3", "TakenAlone": "1", "CounterMask": "0", "Invert": "0", @@ -3736,8 +3736,8 @@ "EventCode": "0xd0", "UMask": "0x06", "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", - "BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES", - "PublicDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES", + "BriefDescription": "Counts the number of stores uops retired.", + "PublicDescription": "Counts the number of stores uops retired.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", @@ -4157,6 +4157,106 @@ "PDISTCounter": "NA", "Speculative": "0" }, + { + "EventCode": "0xe0", + "UMask": "0x02", + "EventName": "MISC_RETIRED1.LFENCE", + "BriefDescription": "Counts the number of LFENCE instructions retired.", + "PublicDescription": "Counts the number of LFENCE instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe0", + "UMask": "0xff", + "EventName": "MISC_RETIRED1.CL_INST", + "BriefDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.", + "PublicDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe1", + "UMask": "0x10", + "EventName": "MISC_RETIRED2.KEYLOCKER_ACCESS", + "BriefDescription": "Counts the number of accesses to KeyLocker cache.", + "PublicDescription": "Counts the number of accesses to KeyLocker cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe1", + "UMask": "0x11", + "EventName": "MISC_RETIRED2.KEYLOCKER_MISS", + "BriefDescription": "Counts the number of misses to KeyLocker cache.", + "PublicDescription": "Counts the number of misses to KeyLocker cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, { "EventCode": "0xe4", "UMask": "0x01", diff --git a/GRR/events/grandridge_uncore.json b/GRR/events/grandridge_uncore.json index 82ae6c5b..eccd682e 100644 --- a/GRR/events/grandridge_uncore.json +++ b/GRR/events/grandridge_uncore.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Grand Ridge Base Transceiver Station Family - V1.10", - "DatePublished": "08/28/2025", - "Version": "1.10", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Grand Ridge Base Transceiver Station Family - V1.11", + "DatePublished": "01/13/2026", + "Version": "1.11", "Legend": "" }, "Events": [ diff --git a/GRR/events/grandridge_uncore_experimental.json b/GRR/events/grandridge_uncore_experimental.json index c16b90f0..ca6adebc 100644 --- a/GRR/events/grandridge_uncore_experimental.json +++ b/GRR/events/grandridge_uncore_experimental.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Grand Ridge Base Transceiver Station Family - V1.10", - "DatePublished": "08/28/2025", - "Version": "1.10", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Grand Ridge Base Transceiver Station Family - V1.11", + "DatePublished": "01/13/2026", + "Version": "1.11", "Legend": "" }, "Events": [ diff --git a/LNL/events/lunarlake_lioncove_core.json b/LNL/events/lunarlake_lioncove_core.json index 0823b168..6d573d18 100644 --- a/LNL/events/lunarlake_lioncove_core.json +++ b/LNL/events/lunarlake_lioncove_core.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.20", - "DatePublished": "11/17/2025", - "Version": "1.20", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.21", + "DatePublished": "01/13/2026", + "Version": "1.21", "Legend": "" }, "Events": [ diff --git a/LNL/events/lunarlake_skymont_core.json b/LNL/events/lunarlake_skymont_core.json index f43eb698..06806696 100644 --- a/LNL/events/lunarlake_skymont_core.json +++ b/LNL/events/lunarlake_skymont_core.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.20", - "DatePublished": "11/17/2025", - "Version": "1.20", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.21", + "DatePublished": "01/13/2026", + "Version": "1.21", "Legend": "" }, "Events": [ @@ -39,8 +39,8 @@ "UMask": "0x02", "UMaskExt": "0x00", "EventName": "CPU_CLK_UNHALTED.CORE", - "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles.", - "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles.", + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]", + "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]", "Counter": "Fixed counter 1", "PEBScounters": "33", "SampleAfterValue": "2000003", @@ -7815,8 +7815,8 @@ "UMask": "0x10", "UMaskExt": "0x00", "EventName": "MISC_RETIRED2.KEYLOCKER_ACCESS", - "BriefDescription": "Counts the number of accesses to KeyLocker cache.", - "PublicDescription": "Counts the number of accesses to KeyLocker cache.", + "BriefDescription": "This event is deprecated.", + "PublicDescription": "This event is deprecated.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", @@ -7832,7 +7832,7 @@ "L1_Hit_Indication": "0", "Errata": "null", "Offcore": "0", - "Deprecated": "0", + "Deprecated": "1", "Equal": "0", "PDISTCounter": "NA", "Speculative": "0" @@ -7842,8 +7842,8 @@ "UMask": "0x11", "UMaskExt": "0x00", "EventName": "MISC_RETIRED2.KEYLOCKER_MISS", - "BriefDescription": "Counts the number of misses to KeyLocker cache.", - "PublicDescription": "Counts the number of misses to KeyLocker cache.", + "BriefDescription": "This event is deprecated.", + "PublicDescription": "This event is deprecated.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", @@ -7859,7 +7859,7 @@ "L1_Hit_Indication": "0", "Errata": "null", "Offcore": "0", - "Deprecated": "0", + "Deprecated": "1", "Equal": "0", "PDISTCounter": "NA", "Speculative": "0" diff --git a/LNL/events/lunarlake_uncore.json b/LNL/events/lunarlake_uncore.json index 3e14dd67..9e755e2c 100644 --- a/LNL/events/lunarlake_uncore.json +++ b/LNL/events/lunarlake_uncore.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.20", - "DatePublished": "11/17/2025", - "Version": "1.20", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.21", + "DatePublished": "01/13/2026", + "Version": "1.21", "Legend": "" }, "Events": [ diff --git a/LNL/events/lunarlake_uncore_experimental.json b/LNL/events/lunarlake_uncore_experimental.json index 2a96c05c..c900bc5c 100644 --- a/LNL/events/lunarlake_uncore_experimental.json +++ b/LNL/events/lunarlake_uncore_experimental.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.20", - "DatePublished": "11/17/2025", - "Version": "1.20", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.21", + "DatePublished": "01/13/2026", + "Version": "1.21", "Legend": "" }, "Events": [ diff --git a/MTL/events/meteorlake_crestmont_core.json b/MTL/events/meteorlake_crestmont_core.json index 921ba995..6e57b1fd 100644 --- a/MTL/events/meteorlake_crestmont_core.json +++ b/MTL/events/meteorlake_crestmont_core.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Meteor Lake performance hybrid architecture - V1.19", - "DatePublished": "11/17/2025", - "Version": "1.19", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Meteor Lake performance hybrid architecture - V1.20", + "DatePublished": "01/13/2026", + "Version": "1.20", "Legend": "" }, "Events": [ @@ -11,8 +11,8 @@ "EventCode": "0x00", "UMask": "0x01", "EventName": "INST_RETIRED.ANY", - "BriefDescription": "Fixed Counter: Counts the number of instructions retired", - "PublicDescription": "Fixed Counter: Counts the number of instructions retired", + "BriefDescription": "Fixed Counter: Counts the number of instructions retired.", + "PublicDescription": "Fixed Counter: Counts the number of instructions retired.", "Counter": "Fixed counter 0", "PEBScounters": "32", "SampleAfterValue": "2000003", @@ -36,8 +36,8 @@ "EventCode": "0x00", "UMask": "0x02", "EventName": "CPU_CLK_UNHALTED.CORE", - "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", - "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]", + "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]", "Counter": "Fixed counter 1", "PEBScounters": "33", "SampleAfterValue": "2000003", @@ -86,8 +86,8 @@ "EventCode": "0x00", "UMask": "0x03", "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles", - "PublicDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles", + "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles.", + "PublicDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles.", "Counter": "Fixed counter 2", "PEBScounters": "34", "SampleAfterValue": "2000003", diff --git a/MTL/events/meteorlake_redwoodcove_core.json b/MTL/events/meteorlake_redwoodcove_core.json index acf7a9c3..01129bff 100644 --- a/MTL/events/meteorlake_redwoodcove_core.json +++ b/MTL/events/meteorlake_redwoodcove_core.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Meteor Lake performance hybrid architecture - V1.19", - "DatePublished": "11/17/2025", - "Version": "1.19", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Meteor Lake performance hybrid architecture - V1.20", + "DatePublished": "01/13/2026", + "Version": "1.20", "Legend": "" }, "Events": [ diff --git a/MTL/events/meteorlake_uncore.json b/MTL/events/meteorlake_uncore.json index 2064371e..2863a552 100644 --- a/MTL/events/meteorlake_uncore.json +++ b/MTL/events/meteorlake_uncore.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Meteor Lake performance hybrid architecture - V1.19", - "DatePublished": "11/17/2025", - "Version": "1.19", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Meteor Lake performance hybrid architecture - V1.20", + "DatePublished": "01/13/2026", + "Version": "1.20", "Legend": "" }, "Events": [ diff --git a/MTL/events/meteorlake_uncore_experimental.json b/MTL/events/meteorlake_uncore_experimental.json index 3edb6dc0..ca7bd201 100644 --- a/MTL/events/meteorlake_uncore_experimental.json +++ b/MTL/events/meteorlake_uncore_experimental.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Meteor Lake performance hybrid architecture - V1.19", - "DatePublished": "11/17/2025", - "Version": "1.19", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Meteor Lake performance hybrid architecture - V1.20", + "DatePublished": "01/13/2026", + "Version": "1.20", "Legend": "" }, "Events": [ diff --git a/PTL/events/pantherlake_cougarcove_core.json b/PTL/events/pantherlake_cougarcove_core.json index 57929169..a884d7d4 100644 --- a/PTL/events/pantherlake_cougarcove_core.json +++ b/PTL/events/pantherlake_cougarcove_core.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.03", - "DatePublished": "11/14/2025", - "Version": "1.03", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.04", + "DatePublished": "01/23/2026", + "Version": "1.04", "Legend": "" }, "Events": [ diff --git a/PTL/events/pantherlake_darkmont_core.json b/PTL/events/pantherlake_darkmont_core.json index bb650201..b6d07212 100644 --- a/PTL/events/pantherlake_darkmont_core.json +++ b/PTL/events/pantherlake_darkmont_core.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.03", - "DatePublished": "11/14/2025", - "Version": "1.03", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.04", + "DatePublished": "01/23/2026", + "Version": "1.04", "Legend": "" }, "Events": [ @@ -39,8 +39,8 @@ "UMask": "0x02", "UMaskExt": "0x00", "EventName": "CPU_CLK_UNHALTED.CORE", - "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles.", - "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles.", + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]", + "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]", "Counter": "Fixed counter 1", "PEBScounters": "33", "SampleAfterValue": "2000003", @@ -979,6 +979,33 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x24", + "UMask": "0xc8", + "UMaskExt": "0x00", + "EventName": "L2_REQUEST.HWPF", + "BriefDescription": "Counts the number of L2 cache accesses from front door Hardware Prefetch requests. Does not include rejects or recycles, per core event.", + "PublicDescription": "Counts the number of L2 cache accesses from front door Hardware Prefetch requests. Does not include rejects or recycles, per core event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x24", "UMask": "0xff", @@ -2140,6 +2167,33 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x75", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "SERIALIZATION.COLOR_STALLS", + "BriefDescription": "Counts the number issue slots not consumed due to a color request for an FCW or MXCSR control register when all 4 colors (copies) are already in use.", + "PublicDescription": "Counts the number issue slots not consumed due to a color request for an FCW or MXCSR control register when all 4 colors (copies) are already in use.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x80", "UMask": "0x01", @@ -3436,6 +3490,87 @@ "PDISTCounter": "0,1", "Speculative": "0" }, + { + "EventCode": "0xc4", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.COND_TAKEN_BWD", + "BriefDescription": "Counts the number of taken backward conditional branch instructions retired.", + "PublicDescription": "Counts the number of taken backward conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.COND_TAKEN_FWD", + "BriefDescription": "Counts the number of taken forward conditional branch instructions retired.", + "PublicDescription": "Counts the number of taken forward conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.COND_TAKEN", + "BriefDescription": "Counts the number of taken conditional branch instructions retired.", + "PublicDescription": "Counts the number of taken conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, { "EventCode": "0xc4", "UMask": "0x04", @@ -3463,6 +3598,33 @@ "PDISTCounter": "0,1", "Speculative": "0" }, + { + "EventCode": "0xc4", + "UMask": "0x07", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.COND", + "BriefDescription": "Counts the number of conditional branch instructions retired.", + "PublicDescription": "Counts the number of conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, { "EventCode": "0xc4", "UMask": "0x30", @@ -3490,6 +3652,114 @@ "PDISTCounter": "0,1", "Speculative": "0" }, + { + "EventCode": "0xc4", + "UMask": "0x50", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.ALL_NEAR_IND", + "BriefDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT]", + "PublicDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x50", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.NEAR_INDIRECT", + "BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired. [This event is alias to BR_INST_RETIRED.ALL_NEAR_IND]", + "PublicDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired. [This event is alias to BR_INST_RETIRED.ALL_NEAR_IND]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x58", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.ALL_NEAR_IND_OR_RET", + "BriefDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_OR_RETURN]", + "PublicDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_OR_RETURN]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x58", + "UMaskExt": "0x00", + "EventName": "BR_INST_RETIRED.NEAR_INDIRECT_OR_RETURN", + "BriefDescription": "Counts the number of near indirect JMP, near indirect CALL, and RET branch instructions retired. [This event is alias to BR_INST_RETIRED.ALL_NEAR_IND_OR_RET]", + "PublicDescription": "Counts the number of near indirect JMP, near indirect CALL, and RET branch instructions retired. [This event is alias to BR_INST_RETIRED.ALL_NEAR_IND_OR_RET]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, { "EventCode": "0xc4", "UMask": "0xfb", @@ -4224,8 +4494,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 1024.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 1024.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", @@ -4305,8 +4575,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 2048.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 2048.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", diff --git a/PTL/events/pantherlake_uncore.json b/PTL/events/pantherlake_uncore.json index 5230fb8d..f358e543 100644 --- a/PTL/events/pantherlake_uncore.json +++ b/PTL/events/pantherlake_uncore.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.03", - "DatePublished": "11/14/2025", - "Version": "1.03", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.04", + "DatePublished": "01/23/2026", + "Version": "1.04", "Legend": "" }, "Events": [ diff --git a/SRF/events/sierraforest_core.json b/SRF/events/sierraforest_core.json index 7abf4bc1..fdb00981 100644 --- a/SRF/events/sierraforest_core.json +++ b/SRF/events/sierraforest_core.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with E-cores - V1.14", - "DatePublished": "11/19/2025", - "Version": "1.14", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with E-cores - V1.15", + "DatePublished": "01/13/2026", + "Version": "1.15", "Legend": "" }, "Events": [ @@ -11,8 +11,8 @@ "EventCode": "0x00", "UMask": "0x01", "EventName": "INST_RETIRED.ANY", - "BriefDescription": "Fixed Counter: Counts the number of instructions retired", - "PublicDescription": "Fixed Counter: Counts the number of instructions retired", + "BriefDescription": "Fixed Counter: Counts the number of instructions retired.", + "PublicDescription": "Fixed Counter: Counts the number of instructions retired.", "Counter": "Fixed counter 0", "PEBScounters": "32", "SampleAfterValue": "2000003", @@ -36,8 +36,8 @@ "EventCode": "0x00", "UMask": "0x02", "EventName": "CPU_CLK_UNHALTED.CORE", - "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", - "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]", + "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]", "Counter": "Fixed counter 1", "PEBScounters": "33", "SampleAfterValue": "2000003", @@ -86,8 +86,8 @@ "EventCode": "0x00", "UMask": "0x03", "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles", - "PublicDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles", + "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles.", + "PublicDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles.", "Counter": "Fixed counter 2", "PEBScounters": "34", "SampleAfterValue": "2000003", @@ -4482,6 +4482,106 @@ "PDISTCounter": "NA", "Speculative": "0" }, + { + "EventCode": "0xe0", + "UMask": "0x02", + "EventName": "MISC_RETIRED1.LFENCE", + "BriefDescription": "Counts the number of LFENCE instructions retired.", + "PublicDescription": "Counts the number of LFENCE instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe0", + "UMask": "0xff", + "EventName": "MISC_RETIRED1.CL_INST", + "BriefDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.", + "PublicDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe1", + "UMask": "0x10", + "EventName": "MISC_RETIRED2.KEYLOCKER_ACCESS", + "BriefDescription": "Counts the number of accesses to KeyLocker cache.", + "PublicDescription": "Counts the number of accesses to KeyLocker cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe1", + "UMask": "0x11", + "EventName": "MISC_RETIRED2.KEYLOCKER_MISS", + "BriefDescription": "Counts the number of misses to KeyLocker cache.", + "PublicDescription": "Counts the number of misses to KeyLocker cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, { "EventCode": "0xe4", "UMask": "0x01", diff --git a/SRF/events/sierraforest_uncore.json b/SRF/events/sierraforest_uncore.json index 069516f9..305b103e 100644 --- a/SRF/events/sierraforest_uncore.json +++ b/SRF/events/sierraforest_uncore.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with E-cores - V1.14", - "DatePublished": "11/19/2025", - "Version": "1.14", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with E-cores - V1.15", + "DatePublished": "01/13/2026", + "Version": "1.15", "Legend": "" }, "Events": [ diff --git a/SRF/events/sierraforest_uncore_experimental.json b/SRF/events/sierraforest_uncore_experimental.json index 6d67851e..4196c7b7 100644 --- a/SRF/events/sierraforest_uncore_experimental.json +++ b/SRF/events/sierraforest_uncore_experimental.json @@ -1,9 +1,9 @@ { "Header": { - "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with E-cores - V1.14", - "DatePublished": "11/19/2025", - "Version": "1.14", + "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with E-cores - V1.15", + "DatePublished": "01/13/2026", + "Version": "1.15", "Legend": "" }, "Events": [ diff --git a/mapfile.csv b/mapfile.csv index df91ea62..7d5d289e 100644 --- a/mapfile.csv +++ b/mapfile.csv @@ -157,48 +157,48 @@ GenuineIntel-6-6C,V1.30,/ICX/events/icelakex_uncore_experimental.json,uncore exp GenuineIntel-6-6C,V1.1,/ICX/metrics/icelakex_metrics.json,metrics,,, GenuineIntel-6-96,V1.05,/EHL/events/elkhartlake_core.json,core,,, GenuineIntel-6-9C,V1.05,/EHL/events/elkhartlake_core.json,core,,, -GenuineIntel-6-97,V1.36,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom -GenuineIntel-6-97,V1.36,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core -GenuineIntel-6-97,V1.36,/ADL/events/alderlake_uncore.json,uncore,,, -GenuineIntel-6-97,V1.36,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-97,V1.37,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom +GenuineIntel-6-97,V1.37,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core +GenuineIntel-6-97,V1.37,/ADL/events/alderlake_uncore.json,uncore,,, +GenuineIntel-6-97,V1.37,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-97,V1.1,/ADL/metrics/alderlake_metrics_goldencove_core.json,metrics,0x40,0x000001,Core -GenuineIntel-6-9A,V1.36,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom -GenuineIntel-6-9A,V1.36,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core -GenuineIntel-6-9A,V1.36,/ADL/events/alderlake_uncore.json,uncore,,, -GenuineIntel-6-9A,V1.36,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-9A,V1.37,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom +GenuineIntel-6-9A,V1.37,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core +GenuineIntel-6-9A,V1.37,/ADL/events/alderlake_uncore.json,uncore,,, +GenuineIntel-6-9A,V1.37,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-9A,V1.1,/ADL/metrics/alderlake_metrics_goldencove_core.json,metrics,0x40,0x000001,Core -GenuineIntel-6-B7,V1.36,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom -GenuineIntel-6-B7,V1.36,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core -GenuineIntel-6-B7,V1.36,/ADL/events/alderlake_uncore.json,uncore,,, -GenuineIntel-6-B7,V1.36,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-B7,V1.37,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom +GenuineIntel-6-B7,V1.37,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core +GenuineIntel-6-B7,V1.37,/ADL/events/alderlake_uncore.json,uncore,,, +GenuineIntel-6-B7,V1.37,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-B7,V1.1,/ADL/metrics/alderlake_metrics_goldencove_core.json,metrics,0x40,0x000001,Core -GenuineIntel-6-BA,V1.36,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom -GenuineIntel-6-BA,V1.36,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core -GenuineIntel-6-BA,V1.36,/ADL/events/alderlake_uncore.json,uncore,,, -GenuineIntel-6-BA,V1.36,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-BA,V1.37,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom +GenuineIntel-6-BA,V1.37,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core +GenuineIntel-6-BA,V1.37,/ADL/events/alderlake_uncore.json,uncore,,, +GenuineIntel-6-BA,V1.37,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-BA,V1.1,/ADL/metrics/alderlake_metrics_goldencove_core.json,metrics,0x40,0x000001,Core -GenuineIntel-6-BF,V1.36,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom -GenuineIntel-6-BF,V1.36,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core -GenuineIntel-6-BF,V1.36,/ADL/events/alderlake_uncore.json,uncore,,, -GenuineIntel-6-BF,V1.36,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-BF,V1.37,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom +GenuineIntel-6-BF,V1.37,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core +GenuineIntel-6-BF,V1.37,/ADL/events/alderlake_uncore.json,uncore,,, +GenuineIntel-6-BF,V1.37,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-BF,V1.1,/ADL/metrics/alderlake_metrics_goldencove_core.json,metrics,0x40,0x000001,Core -GenuineIntel-6-BE,V1.36,/ADL/events/alderlake_gracemont_core.json,core,,, -GenuineIntel-6-BE,V1.36,/ADL/events/alderlake_uncore.json,uncore,,, -GenuineIntel-6-BE,V1.36,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, -GenuineIntel-6-AA,V1.19,/MTL/events/meteorlake_crestmont_core.json,hybridcore,0x20,0x000002,Atom -GenuineIntel-6-AA,V1.19,/MTL/events/meteorlake_redwoodcove_core.json,hybridcore,0x40,0x000002,Core -GenuineIntel-6-AA,V1.19,/MTL/events/meteorlake_uncore.json,uncore,,, -GenuineIntel-6-AA,V1.19,/MTL/events/meteorlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-BE,V1.37,/ADL/events/alderlake_gracemont_core.json,core,,, +GenuineIntel-6-BE,V1.37,/ADL/events/alderlake_uncore.json,uncore,,, +GenuineIntel-6-BE,V1.37,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-AA,V1.20,/MTL/events/meteorlake_crestmont_core.json,hybridcore,0x20,0x000002,Atom +GenuineIntel-6-AA,V1.20,/MTL/events/meteorlake_redwoodcove_core.json,hybridcore,0x40,0x000002,Core +GenuineIntel-6-AA,V1.20,/MTL/events/meteorlake_uncore.json,uncore,,, +GenuineIntel-6-AA,V1.20,/MTL/events/meteorlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-AA,V1.1,/MTL/metrics/meteorlake_metrics_redwoodcove_core.json,metrics,0x40,0x000002,Core -GenuineIntel-6-AC,V1.19,/MTL/events/meteorlake_crestmont_core.json,hybridcore,0x20,0x000002,Atom -GenuineIntel-6-AC,V1.19,/MTL/events/meteorlake_redwoodcove_core.json,hybridcore,0x40,0x000002,Core -GenuineIntel-6-AC,V1.19,/MTL/events/meteorlake_uncore.json,uncore,,, -GenuineIntel-6-AC,V1.19,/MTL/events/meteorlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-AC,V1.20,/MTL/events/meteorlake_crestmont_core.json,hybridcore,0x20,0x000002,Atom +GenuineIntel-6-AC,V1.20,/MTL/events/meteorlake_redwoodcove_core.json,hybridcore,0x40,0x000002,Core +GenuineIntel-6-AC,V1.20,/MTL/events/meteorlake_uncore.json,uncore,,, +GenuineIntel-6-AC,V1.20,/MTL/events/meteorlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-AC,V1.1,/MTL/metrics/meteorlake_metrics_redwoodcove_core.json,metrics,0x40,0x000002,Core -GenuineIntel-6-B5,V1.19,/MTL/events/meteorlake_crestmont_core.json,hybridcore,0x20,0x000002,Atom -GenuineIntel-6-B5,V1.19,/MTL/events/meteorlake_redwoodcove_core.json,hybridcore,0x40,0x000002,Core -GenuineIntel-6-B5,V1.19,/MTL/events/meteorlake_uncore.json,uncore,,, -GenuineIntel-6-B5,V1.19,/MTL/events/meteorlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-B5,V1.20,/MTL/events/meteorlake_crestmont_core.json,hybridcore,0x20,0x000002,Atom +GenuineIntel-6-B5,V1.20,/MTL/events/meteorlake_redwoodcove_core.json,hybridcore,0x40,0x000002,Core +GenuineIntel-6-B5,V1.20,/MTL/events/meteorlake_uncore.json,uncore,,, +GenuineIntel-6-B5,V1.20,/MTL/events/meteorlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-B5,V1.1,/MTL/metrics/meteorlake_metrics_redwoodcove_core.json,metrics,0x40,0x000002,Core GenuineIntel-6-AD,V1.17,/GNR/events/graniterapids_core.json,core,,, GenuineIntel-6-AD,V1.17,/GNR/events/graniterapids_uncore.json,uncore,,, @@ -210,31 +210,31 @@ GenuineIntel-6-AE,V1.17,/GNR/events/graniterapids_uncore.json,uncore,,, GenuineIntel-6-AE,V1.17,/GNR/events/graniterapids_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-AE,V1.2,/GNR/metrics/graniterapids_metrics.json,metrics,,, GenuineIntel-6-AE,V1.08,/GNR/metrics/graniterapids_retire_latency.json,retire latency,,, -GenuineIntel-6-AF,V1.14,/SRF/events/sierraforest_core.json,core,,, -GenuineIntel-6-AF,V1.14,/SRF/events/sierraforest_uncore.json,uncore,,, -GenuineIntel-6-AF,V1.14,/SRF/events/sierraforest_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-AF,V1.15,/SRF/events/sierraforest_core.json,core,,, +GenuineIntel-6-AF,V1.15,/SRF/events/sierraforest_uncore.json,uncore,,, +GenuineIntel-6-AF,V1.15,/SRF/events/sierraforest_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-AF,V1.02,/SRF/metrics/sierraforest_metrics.json,metrics,,, -GenuineIntel-6-B6,V1.10,/GRR/events/grandridge_core.json,core,,, -GenuineIntel-6-B6,V1.10,/GRR/events/grandridge_uncore.json,uncore,,, -GenuineIntel-6-B6,V1.10,/GRR/events/grandridge_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-B6,V1.11,/GRR/events/grandridge_core.json,core,,, +GenuineIntel-6-B6,V1.11,/GRR/events/grandridge_uncore.json,uncore,,, +GenuineIntel-6-B6,V1.11,/GRR/events/grandridge_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-B6,V1.02,/GRR/metrics/grandridge_metrics.json,metrics,,, -GenuineIntel-6-BD,V1.20,/LNL/events/lunarlake_skymont_core.json,hybridcore,0x20,0x000003,Atom -GenuineIntel-6-BD,V1.20,/LNL/events/lunarlake_lioncove_core.json,hybridcore,0x40,0x000003,Core -GenuineIntel-6-BD,V1.20,/LNL/events/lunarlake_uncore.json,uncore,,, -GenuineIntel-6-BD,V1.20,/LNL/events/lunarlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-BD,V1.21,/LNL/events/lunarlake_skymont_core.json,hybridcore,0x20,0x000003,Atom +GenuineIntel-6-BD,V1.21,/LNL/events/lunarlake_lioncove_core.json,hybridcore,0x40,0x000003,Core +GenuineIntel-6-BD,V1.21,/LNL/events/lunarlake_uncore.json,uncore,,, +GenuineIntel-6-BD,V1.21,/LNL/events/lunarlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-BD,V1.1,/LNL/metrics/lunarlake_metrics_lioncove_core.json,metrics,0x40,0x000003,Core -GenuineIntel-6-C5,V1.15,/ARL/events/arrowlake_skymont_core.json,hybridcore,0x20,0x000003,Atom -GenuineIntel-6-C5,V1.15,/ARL/events/arrowlake_crestmont_core.json,hybridcore,0x20,0x000002,LowPower_Atom -GenuineIntel-6-C5,V1.15,/ARL/events/arrowlake_lioncove_core.json,hybridcore,0x40,0x000003,Core -GenuineIntel-6-C5,V1.15,/ARL/events/arrowlake_uncore.json,uncore,,, -GenuineIntel-6-C5,V1.15,/ARL/events/arrowlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-C5,V1.16,/ARL/events/arrowlake_skymont_core.json,hybridcore,0x20,0x000003,Atom +GenuineIntel-6-C5,V1.16,/ARL/events/arrowlake_crestmont_core.json,hybridcore,0x20,0x000002,LowPower_Atom +GenuineIntel-6-C5,V1.16,/ARL/events/arrowlake_lioncove_core.json,hybridcore,0x40,0x000003,Core +GenuineIntel-6-C5,V1.16,/ARL/events/arrowlake_uncore.json,uncore,,, +GenuineIntel-6-C5,V1.16,/ARL/events/arrowlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-C5,V1.1,/ARL/metrics/arrowlake_metrics_lioncove_core.json,metrics,0x40,0x000003,Core -GenuineIntel-6-C6,V1.15,/ARL/events/arrowlake_skymont_core.json,hybridcore,0x20,0x000003,Atom -GenuineIntel-6-C6,V1.15,/ARL/events/arrowlake_lioncove_core.json,hybridcore,0x40,0x000003,Core -GenuineIntel-6-C6,V1.15,/ARL/events/arrowlake_uncore.json,uncore,,, -GenuineIntel-6-C6,V1.15,/ARL/events/arrowlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-C6,V1.16,/ARL/events/arrowlake_skymont_core.json,hybridcore,0x20,0x000003,Atom +GenuineIntel-6-C6,V1.16,/ARL/events/arrowlake_lioncove_core.json,hybridcore,0x40,0x000003,Core +GenuineIntel-6-C6,V1.16,/ARL/events/arrowlake_uncore.json,uncore,,, +GenuineIntel-6-C6,V1.16,/ARL/events/arrowlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-C6,V1.1,/ARL/metrics/arrowlake_metrics_lioncove_core.json,metrics,0x40,0x000003,Core -GenuineIntel-6-CC,V1.03,/PTL/events/pantherlake_darkmont_core.json,hybridcore,0x20,0x000004,Atom -GenuineIntel-6-CC,V1.03,/PTL/events/pantherlake_cougarcove_core.json,hybridcore,0x40,0x000004,Core -GenuineIntel-6-CC,V1.03,/PTL/events/pantherlake_uncore.json,uncore,,, +GenuineIntel-6-CC,V1.04,/PTL/events/pantherlake_darkmont_core.json,hybridcore,0x20,0x000004,Atom +GenuineIntel-6-CC,V1.04,/PTL/events/pantherlake_cougarcove_core.json,hybridcore,0x40,0x000004,Core +GenuineIntel-6-CC,V1.04,/PTL/events/pantherlake_uncore.json,uncore,,, GenuineIntel-6-DD,V1.00,/CWF/events/clearwaterforest_core.json,core,,,