diff --git a/arch/src/x86_64/cpu_profiles/sapphire-rapids.cpuid.json b/arch/src/x86_64/cpu_profiles/sapphire-rapids.cpuid.json index b3389bf947..b0790bb426 100644 --- a/arch/src/x86_64/cpu_profiles/sapphire-rapids.cpuid.json +++ b/arch/src/x86_64/cpu_profiles/sapphire-rapids.cpuid.json @@ -1182,13 +1182,13 @@ { "leaf": "0xd", "sub_leaf": { - "start": "0x8", - "end": "0x8" + "start": "0x5", + "end": "0x5" }, - "register": "EAX" + "register": "EBX" }, { - "replacements": "0x00000000", + "replacements": "0x00000440", "mask": "0x00000000" } ], @@ -1196,13 +1196,13 @@ { "leaf": "0xd", "sub_leaf": { - "start": "0x9", - "end": "0x9" + "start": "0x6", + "end": "0x6" }, - "register": "EAX" + "register": "EBX" }, { - "replacements": "0x00000008", + "replacements": "0x00000480", "mask": "0x00000000" } ], @@ -1210,13 +1210,13 @@ { "leaf": "0xd", "sub_leaf": { - "start": "0xa", - "end": "0xa" + "start": "0x7", + "end": "0x7" }, - "register": "EAX" + "register": "EBX" }, { - "replacements": "0x00000000", + "replacements": "0x00000680", "mask": "0x00000000" } ], @@ -1227,10 +1227,10 @@ "start": "0x5", "end": "0x5" }, - "register": "EBX" + "register": "ECX" }, { - "replacements": "0x00000440", + "replacements": "0x00000000", "mask": "0x00000000" } ], @@ -1241,10 +1241,10 @@ "start": "0x6", "end": "0x6" }, - "register": "EBX" + "register": "ECX" }, { - "replacements": "0x00000480", + "replacements": "0x00000000", "mask": "0x00000000" } ], @@ -1255,10 +1255,10 @@ "start": "0x7", "end": "0x7" }, - "register": "EBX" + "register": "ECX" }, { - "replacements": "0x00000680", + "replacements": "0x00000000", "mask": "0x00000000" } ], @@ -1269,7 +1269,7 @@ "start": "0x8", "end": "0x8" }, - "register": "EBX" + "register": "EAX" }, { "replacements": "0x00000000", @@ -1280,13 +1280,13 @@ { "leaf": "0xd", "sub_leaf": { - "start": "0x9", - "end": "0x9" + "start": "0x8", + "end": "0x8" }, "register": "EBX" }, { - "replacements": "0x00000a80", + "replacements": "0x00000000", "mask": "0x00000000" } ], @@ -1294,10 +1294,10 @@ { "leaf": "0xd", "sub_leaf": { - "start": "0xa", - "end": "0xa" + "start": "0x8", + "end": "0x8" }, - "register": "EBX" + "register": "ECX" }, { "replacements": "0x00000000", @@ -1308,10 +1308,10 @@ { "leaf": "0xd", "sub_leaf": { - "start": "0x5", - "end": "0x5" + "start": "0x8", + "end": "0x8" }, - "register": "ECX" + "register": "EDX" }, { "replacements": "0x00000000", @@ -1322,8 +1322,36 @@ { "leaf": "0xd", "sub_leaf": { - "start": "0x6", - "end": "0x6" + "start": "0x9", + "end": "0x9" + }, + "register": "EAX" + }, + { + "replacements": "0x00000008", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0xd", + "sub_leaf": { + "start": "0x9", + "end": "0x9" + }, + "register": "EBX" + }, + { + "replacements": "0x00000a80", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0xd", + "sub_leaf": { + "start": "0x9", + "end": "0x9" }, "register": "ECX" }, @@ -1336,10 +1364,10 @@ { "leaf": "0xd", "sub_leaf": { - "start": "0x7", - "end": "0x7" + "start": "0xa", + "end": "0xa" }, - "register": "ECX" + "register": "EAX" }, { "replacements": "0x00000000", @@ -1350,10 +1378,10 @@ { "leaf": "0xd", "sub_leaf": { - "start": "0x8", - "end": "0x8" + "start": "0xa", + "end": "0xa" }, - "register": "ECX" + "register": "EBX" }, { "replacements": "0x00000000", @@ -1364,8 +1392,8 @@ { "leaf": "0xd", "sub_leaf": { - "start": "0x9", - "end": "0x9" + "start": "0xa", + "end": "0xa" }, "register": "ECX" }, @@ -1381,7 +1409,7 @@ "start": "0xa", "end": "0xa" }, - "register": "ECX" + "register": "EDX" }, { "replacements": "0x00000000", @@ -1542,6 +1570,20 @@ "mask": "0x00000000" } ], + [ + { + "leaf": "0xd", + "sub_leaf": { + "start": "0xd", + "end": "0xd" + }, + "register": "EDX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], [ { "leaf": "0xd", @@ -1603,7 +1645,7 @@ "leaf": "0xd", "sub_leaf": { "start": "0xf", - "end": "0x10" + "end": "0xf" }, "register": "EAX" }, @@ -1616,13 +1658,13 @@ { "leaf": "0xd", "sub_leaf": { - "start": "0x11", - "end": "0x11" + "start": "0xf", + "end": "0xf" }, - "register": "EAX" + "register": "EBX" }, { - "replacements": "0x00000040", + "replacements": "0x00000000", "mask": "0x00000000" } ], @@ -1630,13 +1672,13 @@ { "leaf": "0xd", "sub_leaf": { - "start": "0x12", - "end": "0x12" + "start": "0xf", + "end": "0xf" }, - "register": "EAX" + "register": "ECX" }, { - "replacements": "0x00002000", + "replacements": "0x00000000", "mask": "0x00000000" } ], @@ -1644,8 +1686,22 @@ { "leaf": "0xd", "sub_leaf": { - "start": "0x13", - "end": "0x3f" + "start": "0xf", + "end": "0xf" + }, + "register": "EDX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0xd", + "sub_leaf": { + "start": "0x10", + "end": "0x10" }, "register": "EAX" }, @@ -1658,7 +1714,7 @@ { "leaf": "0xd", "sub_leaf": { - "start": "0xf", + "start": "0x10", "end": "0x10" }, "register": "EBX" @@ -1668,6 +1724,34 @@ "mask": "0x00000000" } ], + [ + { + "leaf": "0xd", + "sub_leaf": { + "start": "0x10", + "end": "0x10" + }, + "register": "ECX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0xd", + "sub_leaf": { + "start": "0x10", + "end": "0x10" + }, + "register": "EDX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], [ { "leaf": "0xd", @@ -1675,10 +1759,10 @@ "start": "0x11", "end": "0x11" }, - "register": "EBX" + "register": "EAX" }, { - "replacements": "0x00000ac0", + "replacements": "0x00000040", "mask": "0x00000000" } ], @@ -1689,10 +1773,10 @@ "start": "0x12", "end": "0x12" }, - "register": "EBX" + "register": "EAX" }, { - "replacements": "0x00000b00", + "replacements": "0x00002000", "mask": "0x00000000" } ], @@ -1703,7 +1787,7 @@ "start": "0x13", "end": "0x3f" }, - "register": "EBX" + "register": "EAX" }, { "replacements": "0x00000000", @@ -1714,10 +1798,38 @@ { "leaf": "0xd", "sub_leaf": { - "start": "0xf", - "end": "0x10" + "start": "0x11", + "end": "0x11" }, - "register": "ECX" + "register": "EBX" + }, + { + "replacements": "0x00000ac0", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0xd", + "sub_leaf": { + "start": "0x12", + "end": "0x12" + }, + "register": "EBX" + }, + { + "replacements": "0x00000b00", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0xd", + "sub_leaf": { + "start": "0x13", + "end": "0x3f" + }, + "register": "EBX" }, { "replacements": "0x00000000", diff --git a/arch/src/x86_64/cpu_profiles/sapphire-rapids.msr.json b/arch/src/x86_64/cpu_profiles/sapphire-rapids.msr.json index cd2b7a5a97..c9b5d42089 100644 --- a/arch/src/x86_64/cpu_profiles/sapphire-rapids.msr.json +++ b/arch/src/x86_64/cpu_profiles/sapphire-rapids.msr.json @@ -203,4 +203,4 @@ "0xc0000102", "0xc0000103" ] -} +} \ No newline at end of file diff --git a/arch/src/x86_64/cpu_profiles/skylake.cpuid.json b/arch/src/x86_64/cpu_profiles/skylake.cpuid.json index 48c3f94ccd..bbe3ec73a8 100644 --- a/arch/src/x86_64/cpu_profiles/skylake.cpuid.json +++ b/arch/src/x86_64/cpu_profiles/skylake.cpuid.json @@ -1238,13 +1238,13 @@ { "leaf": "0xd", "sub_leaf": { - "start": "0x8", - "end": "0x8" + "start": "0x5", + "end": "0x5" }, - "register": "EAX" + "register": "EBX" }, { - "replacements": "0x00000000", + "replacements": "0x00000440", "mask": "0x00000000" } ], @@ -1252,13 +1252,13 @@ { "leaf": "0xd", "sub_leaf": { - "start": "0x9", - "end": "0x9" + "start": "0x6", + "end": "0x6" }, - "register": "EAX" + "register": "EBX" }, { - "replacements": "0x00000008", + "replacements": "0x00000480", "mask": "0x00000000" } ], @@ -1266,13 +1266,13 @@ { "leaf": "0xd", "sub_leaf": { - "start": "0xa", - "end": "0xa" + "start": "0x7", + "end": "0x7" }, - "register": "EAX" + "register": "EBX" }, { - "replacements": "0x00000000", + "replacements": "0x00000680", "mask": "0x00000000" } ], @@ -1283,10 +1283,10 @@ "start": "0x5", "end": "0x5" }, - "register": "EBX" + "register": "ECX" }, { - "replacements": "0x00000440", + "replacements": "0x00000000", "mask": "0x00000000" } ], @@ -1297,10 +1297,10 @@ "start": "0x6", "end": "0x6" }, - "register": "EBX" + "register": "ECX" }, { - "replacements": "0x00000480", + "replacements": "0x00000000", "mask": "0x00000000" } ], @@ -1311,10 +1311,10 @@ "start": "0x7", "end": "0x7" }, - "register": "EBX" + "register": "ECX" }, { - "replacements": "0x00000680", + "replacements": "0x00000000", "mask": "0x00000000" } ], @@ -1325,7 +1325,7 @@ "start": "0x8", "end": "0x8" }, - "register": "EBX" + "register": "EAX" }, { "replacements": "0x00000000", @@ -1336,13 +1336,13 @@ { "leaf": "0xd", "sub_leaf": { - "start": "0x9", - "end": "0x9" + "start": "0x8", + "end": "0x8" }, "register": "EBX" }, { - "replacements": "0x00000a80", + "replacements": "0x00000000", "mask": "0x00000000" } ], @@ -1350,10 +1350,10 @@ { "leaf": "0xd", "sub_leaf": { - "start": "0xa", - "end": "0xa" + "start": "0x8", + "end": "0x8" }, - "register": "EBX" + "register": "ECX" }, { "replacements": "0x00000000", @@ -1364,10 +1364,10 @@ { "leaf": "0xd", "sub_leaf": { - "start": "0x5", - "end": "0x5" + "start": "0x8", + "end": "0x8" }, - "register": "ECX" + "register": "EDX" }, { "replacements": "0x00000000", @@ -1378,8 +1378,36 @@ { "leaf": "0xd", "sub_leaf": { - "start": "0x6", - "end": "0x6" + "start": "0x9", + "end": "0x9" + }, + "register": "EAX" + }, + { + "replacements": "0x00000008", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0xd", + "sub_leaf": { + "start": "0x9", + "end": "0x9" + }, + "register": "EBX" + }, + { + "replacements": "0x00000a80", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0xd", + "sub_leaf": { + "start": "0x9", + "end": "0x9" }, "register": "ECX" }, @@ -1392,10 +1420,10 @@ { "leaf": "0xd", "sub_leaf": { - "start": "0x7", - "end": "0x7" + "start": "0xa", + "end": "0xa" }, - "register": "ECX" + "register": "EAX" }, { "replacements": "0x00000000", @@ -1406,10 +1434,10 @@ { "leaf": "0xd", "sub_leaf": { - "start": "0x8", - "end": "0x8" + "start": "0xa", + "end": "0xa" }, - "register": "ECX" + "register": "EBX" }, { "replacements": "0x00000000", @@ -1420,8 +1448,8 @@ { "leaf": "0xd", "sub_leaf": { - "start": "0x9", - "end": "0x9" + "start": "0xa", + "end": "0xa" }, "register": "ECX" }, @@ -1437,7 +1465,7 @@ "start": "0xa", "end": "0xa" }, - "register": "ECX" + "register": "EDX" }, { "replacements": "0x00000000", @@ -1542,6 +1570,20 @@ "mask": "0x00000000" } ], + [ + { + "leaf": "0xd", + "sub_leaf": { + "start": "0xd", + "end": "0xd" + }, + "register": "EDX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], [ { "leaf": "0xd", @@ -1603,7 +1645,7 @@ "leaf": "0xd", "sub_leaf": { "start": "0xf", - "end": "0x3f" + "end": "0xf" }, "register": "EAX" }, @@ -1617,7 +1659,7 @@ "leaf": "0xd", "sub_leaf": { "start": "0xf", - "end": "0x3f" + "end": "0xf" }, "register": "EBX" }, @@ -1631,6 +1673,118 @@ "leaf": "0xd", "sub_leaf": { "start": "0xf", + "end": "0xf" + }, + "register": "ECX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0xd", + "sub_leaf": { + "start": "0xf", + "end": "0xf" + }, + "register": "EDX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0xd", + "sub_leaf": { + "start": "0x10", + "end": "0x10" + }, + "register": "EAX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0xd", + "sub_leaf": { + "start": "0x10", + "end": "0x10" + }, + "register": "EBX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0xd", + "sub_leaf": { + "start": "0x10", + "end": "0x10" + }, + "register": "ECX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0xd", + "sub_leaf": { + "start": "0x10", + "end": "0x10" + }, + "register": "EDX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0xd", + "sub_leaf": { + "start": "0x11", + "end": "0x3f" + }, + "register": "EAX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0xd", + "sub_leaf": { + "start": "0x11", + "end": "0x3f" + }, + "register": "EBX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0xd", + "sub_leaf": { + "start": "0x11", "end": "0x3f" }, "register": "ECX" diff --git a/arch/src/x86_64/cpu_profiles/skylake.msr.json b/arch/src/x86_64/cpu_profiles/skylake.msr.json index 5cc3398dc1..eceb91fcda 100644 --- a/arch/src/x86_64/cpu_profiles/skylake.msr.json +++ b/arch/src/x86_64/cpu_profiles/skylake.msr.json @@ -201,4 +201,4 @@ "0xc0000102", "0xc0000103" ] -} +} \ No newline at end of file diff --git a/arch/src/x86_64/cpuid_definitions/intel.rs b/arch/src/x86_64/cpuid_definitions/intel.rs index ee944bbf9d..61517e7e1b 100644 --- a/arch/src/x86_64/cpuid_definitions/intel.rs +++ b/arch/src/x86_64/cpuid_definitions/intel.rs @@ -39,7 +39,7 @@ use super::{ /// a few of the short names and descriptions to be more inline with what is written in the /// aforementioned Intel manual. Finally we decided on a [`ProfilePolicy`] to be set for every /// single [`ValueDefinition`] and manually appended those. -pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<167> = const { +pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<187> = const { CpuidDefinitions([ // ========================================================================================= // Basic CPUID Information @@ -2386,9 +2386,9 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<167> = const { // MSR related ValueDefinition { short: "xcr0_ia32_xss", - description: "XCR0.IA32_XSS (bit 8) used for IA32_XSS", + description: "XCR0.IA32_XSS (bit 8) used for PT in IA32_XSS", bits_range: (8, 8), - policy: ProfilePolicy::Inherit, + policy: ProfilePolicy::Static(0), }, ValueDefinition { short: "xcr0_pkru", @@ -2397,10 +2397,10 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<167> = const { policy: ProfilePolicy::Inherit, }, ValueDefinition { - short: "xcr0_ia32_xss_bits", - description: "XCR0.IA32_XSS (bit 10) used for IA32_XSS", + short: "xcr0_ia32_xss_pasid", + description: "XCR0.IA32_XSS (bit 10) used for PASID in IA32_XSS", bits_range: (10, 10), - policy: ProfilePolicy::Inherit, + policy: ProfilePolicy::Static(0), }, ValueDefinition { short: "xcr0_ia32_xss_cet", @@ -2409,10 +2409,10 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<167> = const { policy: ProfilePolicy::Static(0), }, ValueDefinition { - short: "xcr0_ia32_xss_bits", + short: "xcr0_ia32_xss_hdc", description: "XCR0.IA32_XSS (bit 13) used for IA32_XSS", bits_range: (13, 13), - policy: ProfilePolicy::Inherit, + policy: ProfilePolicy::Static(0), }, ValueDefinition { short: "xcr0_ia32_xss_UINTR", @@ -2421,10 +2421,16 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<167> = const { policy: ProfilePolicy::Static(0), }, ValueDefinition { - short: "xcr0_ia32_xss_bits_15_16", - description: "XCR0.IA32_XSS (bit 15 - 16) used for IA32_XSS", - bits_range: (15, 16), - policy: ProfilePolicy::Inherit, + short: "xcr0_ia32_xss_LBR", + description: "XCR0.IA32_XSS (bit 15) used for LBR in IA32_XSS", + bits_range: (15, 15), + policy: ProfilePolicy::Static(0), + }, + ValueDefinition { + short: "xcr0_ia32_xss_bits_hwp", + description: "XCR0.IA32_XSS (bit 16) used for HWP in IA32_XSS", + bits_range: (16, 16), + policy: ProfilePolicy::Static(0), }, // NOTE: AMX currently requires opt-in, even for the host CPU profile. We still inherit this value for profiles and modify this value at runtime if AMX is not enabled by the user. ValueDefinition { @@ -2562,7 +2568,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<167> = const { short: "xss_pt", description: "PT state, supported", bits_range: (8, 8), - policy: ProfilePolicy::Inherit, + policy: ProfilePolicy::Static(0), }, ValueDefinition { short: "xcr0_bit9", @@ -2574,7 +2580,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<167> = const { short: "xss_pasid", description: "PASID state, supported", bits_range: (10, 10), - policy: ProfilePolicy::Inherit, + policy: ProfilePolicy::Static(0), }, ValueDefinition { short: "xss_cet_u", @@ -2592,7 +2598,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<167> = const { short: "xss_hdc", description: "HDC state, supported", bits_range: (13, 13), - policy: ProfilePolicy::Inherit, + policy: ProfilePolicy::Static(0), }, ValueDefinition { short: "xss_uintr", @@ -2604,13 +2610,13 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<167> = const { short: "xss_lbr", description: "LBR state, supported", bits_range: (15, 15), - policy: ProfilePolicy::Inherit, + policy: ProfilePolicy::Static(0), }, ValueDefinition { short: "xss_hwp", description: "HWP state, supported", bits_range: (16, 16), - policy: ProfilePolicy::Inherit, + policy: ProfilePolicy::Static(0), }, ValueDefinition { short: "xcr0_bits", @@ -2752,7 +2758,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<167> = const { ( Parameters { leaf: 0xd, - sub_leaf: RangeInclusive::new(5, 10), + sub_leaf: RangeInclusive::new(5, 7), register: CpuidReg::EAX, }, ValueDefinitions::new(&[ValueDefinition { @@ -2765,7 +2771,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<167> = const { ( Parameters { leaf: 0xd, - sub_leaf: RangeInclusive::new(5, 10), + sub_leaf: RangeInclusive::new(5, 7), register: CpuidReg::EBX, }, ValueDefinitions::new(&[ValueDefinition { @@ -2778,7 +2784,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<167> = const { ( Parameters { leaf: 0xd, - sub_leaf: RangeInclusive::new(5, 10), + sub_leaf: RangeInclusive::new(5, 7), register: CpuidReg::ECX, }, ValueDefinitions::new(&[ @@ -2802,16 +2808,16 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<167> = const { }, ]), ), - // We leave CET out of CPU profiles for the time being + // Disable PT for CPU profiles ( Parameters { leaf: 0xd, - sub_leaf: RangeInclusive::new(11, 12), + sub_leaf: RangeInclusive::new(8, 8), register: CpuidReg::EAX, }, ValueDefinitions::new(&[ValueDefinition { - short: "0xd-11-12-eax-cet-zero", - description: "This leaf has been zeroed out because CET state components are disabled", + short: "0xd-8-eax-pt-zero", + description: "This leaf has been zeroed out because PT state components are disabled", bits_range: (0, 31), policy: ProfilePolicy::Static(0), }]), @@ -2819,12 +2825,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<167> = const { ( Parameters { leaf: 0xd, - sub_leaf: RangeInclusive::new(11, 12), + sub_leaf: RangeInclusive::new(8, 8), register: CpuidReg::EBX, }, ValueDefinitions::new(&[ValueDefinition { - short: "0xd-11-12-ebx-cet-zero", - description: "This leaf has been zeroed out because CET state components are disabled", + short: "0xd-8-ebx-pt-zero", + description: "This leaf has been zeroed out because PT state components are disabled", bits_range: (0, 31), policy: ProfilePolicy::Static(0), }]), @@ -2832,12 +2838,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<167> = const { ( Parameters { leaf: 0xd, - sub_leaf: RangeInclusive::new(11, 12), + sub_leaf: RangeInclusive::new(8, 8), register: CpuidReg::ECX, }, ValueDefinitions::new(&[ValueDefinition { - short: "0xd-11-12-ecx-cet-zero", - description: "This leaf has been zeroed out because CET state components are disabled", + short: "0xd-8-ecx-pt-zero", + description: "This leaf has been zeroed out because PT state components are disabled", bits_range: (0, 31), policy: ProfilePolicy::Static(0), }]), @@ -2845,12 +2851,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<167> = const { ( Parameters { leaf: 0xd, - sub_leaf: RangeInclusive::new(11, 12), + sub_leaf: RangeInclusive::new(8, 8), register: CpuidReg::EDX, }, ValueDefinitions::new(&[ValueDefinition { - short: "0xd-11-12-edx-cet-zero", - description: "This leaf has been zeroed out because CET state components are disabled", + short: "0xd-8-edx-pt-zero", + description: "This leaf has been zeroed out because PT state components are disabled", bits_range: (0, 31), policy: ProfilePolicy::Static(0), }]), @@ -2858,7 +2864,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<167> = const { ( Parameters { leaf: 0xd, - sub_leaf: RangeInclusive::new(13, 13), + sub_leaf: RangeInclusive::new(9, 9), register: CpuidReg::EAX, }, ValueDefinitions::new(&[ValueDefinition { @@ -2871,7 +2877,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<167> = const { ( Parameters { leaf: 0xd, - sub_leaf: RangeInclusive::new(13, 13), + sub_leaf: RangeInclusive::new(9, 9), register: CpuidReg::EBX, }, ValueDefinitions::new(&[ValueDefinition { @@ -2884,7 +2890,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<167> = const { ( Parameters { leaf: 0xd, - sub_leaf: RangeInclusive::new(13, 13), + sub_leaf: RangeInclusive::new(9, 9), register: CpuidReg::ECX, }, ValueDefinitions::new(&[ @@ -2908,6 +2914,165 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<167> = const { }, ]), ), + // Disable PASID for CPU profiles + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(10, 10), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "0xd-10-eax-pasid-zero", + description: "This leaf has been zeroed out because PASID state components are disabled", + bits_range: (0, 31), + policy: ProfilePolicy::Static(0), + }]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(10, 10), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "0xd-10-ebx-pasid-zero", + description: "This leaf has been zeroed out because PASID state components are disabled", + bits_range: (0, 31), + policy: ProfilePolicy::Static(0), + }]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(10, 10), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "0xd-10-ecx-pasid-zero", + description: "This leaf has been zeroed out because PASID state components are disabled", + bits_range: (0, 31), + policy: ProfilePolicy::Static(0), + }]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(10, 10), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "0xd-10-edx-pasid-zero", + description: "This leaf has been zeroed out because PASID state components are disabled", + bits_range: (0, 31), + policy: ProfilePolicy::Static(0), + }]), + ), + // We leave CET out of CPU profiles for the time being + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(11, 12), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "0xd-11-12-eax-cet-zero", + description: "This leaf has been zeroed out because CET state components are disabled", + bits_range: (0, 31), + policy: ProfilePolicy::Static(0), + }]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(11, 12), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "0xd-11-12-ebx-cet-zero", + description: "This leaf has been zeroed out because CET state components are disabled", + bits_range: (0, 31), + policy: ProfilePolicy::Static(0), + }]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(11, 12), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "0xd-11-12-ecx-cet-zero", + description: "This leaf has been zeroed out because CET state components are disabled", + bits_range: (0, 31), + policy: ProfilePolicy::Static(0), + }]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(11, 12), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "0xd-11-12-edx-cet-zero", + description: "This leaf has been zeroed out because CET state components are disabled", + bits_range: (0, 31), + policy: ProfilePolicy::Static(0), + }]), + ), + // Disable HDC for CPU profiles + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(13, 13), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "0xd-13-eax-edc-zero", + description: "This leaf has been zeroed out because CET state components are disabled", + bits_range: (0, 31), + policy: ProfilePolicy::Static(0), + }]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(13, 13), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "0xd-13-ebx-hdc-zero", + description: "This leaf has been zeroed out because CET state components are disabled", + bits_range: (0, 31), + policy: ProfilePolicy::Static(0), + }]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(13, 13), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "0xd-13-ecx-hdc-zero", + description: "This leaf has been zeroed out because CET state components are disabled", + bits_range: (0, 31), + policy: ProfilePolicy::Static(0), + }]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(13, 13), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "0xd-13-edx-hdc-zero", + description: "This leaf has been zeroed out because CET state components are disabled", + bits_range: (0, 31), + policy: ProfilePolicy::Static(0), + }]), + ), // We decided to disable UINTR for CPU profiles, hence we zero out these sub-leaves ( Parameters { @@ -2961,12 +3126,118 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<167> = const { policy: ProfilePolicy::Static(0), }]), ), + // Disable LBR for CPU Profiles + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(15, 15), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "0xd-eax-lbr-zero", + description: "This leaf has been zeroed out because LBR state components are disabled", + bits_range: (0, 31), + policy: ProfilePolicy::Static(0), + }]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(15, 15), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "0xd-ebx-lbr-zero", + description: "This leaf has been zeroed out because LBR state components are disabled", + bits_range: (0, 31), + policy: ProfilePolicy::Static(0), + }]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(15, 15), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "0xd-ecx-lbr-zero", + description: "This leaf has been zeroed out because LBR state components are disabled", + bits_range: (0, 31), + policy: ProfilePolicy::Static(0), + }]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(15, 15), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "0xd-edx-lbr-zero", + description: "This leaf has been zeroed out because LBR state components are disabled", + bits_range: (0, 31), + policy: ProfilePolicy::Static(0), + }]), + ), + // Disable HWP for CPU profiles + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(16, 16), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "0xd-eax-hwp-zero", + description: "This leaf has been zeroed out because HWP state components are disabled", + bits_range: (0, 31), + policy: ProfilePolicy::Static(0), + }]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(16, 16), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "0xd-ebx-hwp-zero", + description: "This leaf has been zeroed out because HWP state components are disabled", + bits_range: (0, 31), + policy: ProfilePolicy::Static(0), + }]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(16, 16), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "0xd-ecx-hwp-zero", + description: "This leaf has been zeroed out because HWP state components are disabled", + bits_range: (0, 31), + policy: ProfilePolicy::Static(0), + }]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(16, 16), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "0xd-edx-hwp-zero", + description: "This leaf has been zeroed out because HWP state components are disabled", + bits_range: (0, 31), + policy: ProfilePolicy::Static(0), + }]), + ), // NOTE: Sub-leaves 17 & 18 are AMX related and we will alter the adjustments corresponding to // the policy declared here at runtime for those values. ( Parameters { leaf: 0xd, - sub_leaf: RangeInclusive::new(15, 63), + sub_leaf: RangeInclusive::new(17, 63), register: CpuidReg::EAX, }, ValueDefinitions::new(&[ValueDefinition { @@ -2979,7 +3250,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<167> = const { ( Parameters { leaf: 0xd, - sub_leaf: RangeInclusive::new(15, 63), + sub_leaf: RangeInclusive::new(17, 63), register: CpuidReg::EBX, }, ValueDefinitions::new(&[ValueDefinition { @@ -2992,7 +3263,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<167> = const { ( Parameters { leaf: 0xd, - sub_leaf: RangeInclusive::new(15, 63), + sub_leaf: RangeInclusive::new(17, 63), register: CpuidReg::ECX, }, ValueDefinitions::new(&[ diff --git a/arch/src/x86_64/msr_definitions/intel/architectural_msrs.rs b/arch/src/x86_64/msr_definitions/intel/architectural_msrs.rs index 6fd61cc3d2..af7b4e7cc0 100644 --- a/arch/src/x86_64/msr_definitions/intel/architectural_msrs.rs +++ b/arch/src/x86_64/msr_definitions/intel/architectural_msrs.rs @@ -429,13 +429,6 @@ mod permitted_architectural_msrs { const IA32_X2APIC_INIT_COUNT: u32 = 0x838; const IA32_X2APIC_DIV_CONF: u32 = 0x83e; - const IA32_XSS: u32 = 0xda0; - const _IA32_XSS_CPUID_CHECK: () = assert_not_denied_cpuid_feature::<3>(&Parameters { - leaf: 0xd, - sub_leaf: 1..=1, - register: CpuidReg::EAX, - }); - /// Extended Feature Enable const IA32_EFER: u32 = 0xc0000080; @@ -461,7 +454,7 @@ mod permitted_architectural_msrs { register: CpuidReg::ECX, }); - pub(super) const READ_WRITE_IA32_MSRS: [u32; 200] = [ + pub(super) const READ_WRITE_IA32_MSRS: [u32; 199] = [ IA32_TIME_STAMP_COUNTER, IA32_APIC_BASE, IA32_FEATURE_CONTROL, @@ -652,7 +645,6 @@ mod permitted_architectural_msrs { IA32_X2APIC_LVT_ERROR, IA32_X2APIC_INIT_COUNT, IA32_X2APIC_DIV_CONF, - IA32_XSS, IA32_EFER, IA32_STAR, IA32_LSTAR, @@ -705,8 +697,8 @@ mod permitted_architectural_msrs { /// /// The MSRs listed here can be studied further in Table 2.2 in Section 2.1 of the Intel SDM /// Vol. 4 from October 2025 - pub(in crate::x86_64) const PERMITTED_IA32_MSRS: [u32; 243] = const { - let mut permitted = [0u32; 243]; + pub(in crate::x86_64) const PERMITTED_IA32_MSRS: [u32; 242] = const { + let mut permitted = [0u32; 242]; let read_only_len = READ_ONLY_IA32_MSRS.len(); let write_only_len = WRITE_ONLY_IA32_MSRS.len(); let read_write_len = READ_WRITE_IA32_MSRS.len(); @@ -1105,6 +1097,21 @@ mod forbidden_architectural_msrs { const IA32_COPY_PLATFORM_TO_LOCAL: (u32, u32) = (0xd92, 0xd92); const IA32_PASID: (u32, u32) = (0xd93, 0xd93); + + /* + IA32_XSS is a bit problematic: Only never kernels will report it via + KVM_GET_MSR_INDEX_LIST, but CPUID 0xd.0x1.EAX[3] reports that this MSR + exists. + + In order for CPU profiles generated with recent kernels to work with + deployments operating with older kernels, we decide to forbid this MSR + for now even though CPUID indicates that it is available to the guest. + + We consider this OK because we have disabled every single IA32_XSS + related state component in the 0xd CPUID leaves, hence there is no + reason for the guest to want to use this. + */ + const IA32_XSS: (u32, u32) = (0xda0, 0xda0); // Disabled via CPUID for non-host CPU profiles const IA32_PKG_HDC_CTL: (u32, u32) = (0xdb0, 0xdb0); @@ -1270,7 +1277,7 @@ mod forbidden_architectural_msrs { const IA32_UARCH_MISC_CTL: (u32, u32) = (0x1b01, 0x1b01); /// A list of ARCHITECTURAL MSR register addresses that are forbidden for all non-host CPU profiles and also not /// considered MSR-based FEATURE indices by KVM. - pub(in crate::x86_64) const FORBIDDEN_IA32_MSR_RANGES: [(u32, u32); 228] = [ + pub(in crate::x86_64) const FORBIDDEN_IA32_MSR_RANGES: [(u32, u32); 229] = [ IA32_P5_MC_ADDR, IA32_P5_MC_TYPE, // TODO: Not sure about IA32_P5_MC_ADDR & IA32_P5_MC_TYPE @@ -1520,6 +1527,7 @@ mod forbidden_architectural_msrs { // Disabled via CPUID for non-host CPU profiles IA32_COPY_PLATFORM_TO_LOCAL, IA32_PASID, + IA32_XSS, // Disabled via CPUID for non-host CPU profiles IA32_PKG_HDC_CTL, // Disabled via CPUID for non-host CPU profiles diff --git a/arch/src/x86_64/msr_definitions/intel/msr_based_features.rs b/arch/src/x86_64/msr_definitions/intel/msr_based_features.rs index bc36eb8581..e5cb7b214d 100644 --- a/arch/src/x86_64/msr_definitions/intel/msr_based_features.rs +++ b/arch/src/x86_64/msr_definitions/intel/msr_based_features.rs @@ -370,11 +370,13 @@ pub static INTEL_MSR_FEATURE_DEFINITIONS: MsrDefinitions<24> = const { bits_range: (55,55), policy: ProfilePolicy::Inherit }, + // This is only available for relatively recent kernels + // TODO: Revisit this policy ValueDefinition { short: "VM_ENTRY_HARDWARE_EXCEPTIONS", description: "If 1, then software can use VM entry to deliver a hardware exception", bits_range: (56, 56), - policy: ProfilePolicy::Inherit + policy: ProfilePolicy::Static(0) } ]) ), @@ -939,7 +941,7 @@ pub static INTEL_MSR_FEATURE_DEFINITIONS: MsrDefinitions<24> = const { short:"ALLOWED_ZERO_CLEAR_IA32_LBR_CTL", description: "See Intel SDM Vol.3C Section 26.7.1 Table 26-14 (Definitions of Primary VM-Exit Controls)", bits_range: (26, 26), - policy: ProfilePolicy::Inherit + policy: ProfilePolicy::Static(0) }, ValueDefinition { short:"ALLOWED_ZERO_CLEAR_UINV", @@ -1080,7 +1082,7 @@ pub static INTEL_MSR_FEATURE_DEFINITIONS: MsrDefinitions<24> = const { short:"ALLOWED_ONE_CLEAR_IA32_LBR_CTL", description: "See Intel SDM Vol.3C Section 26.7.1 Table 26-14 (Definitions of Primary VM-Exit Controls)", bits_range: (58, 58), - policy: ProfilePolicy::Inherit + policy: ProfilePolicy::Static(0) }, ValueDefinition { short:"ALLOWED_ONE_CLEAR_UINV", @@ -1213,7 +1215,7 @@ pub static INTEL_MSR_FEATURE_DEFINITIONS: MsrDefinitions<24> = const { short:"ALLOWED_ZERO_LOAD_GUEST_IA32_LBR_CTL", description: "See Intel SDM Vol.3C Section 26.8.1 Table 26-17. (Definitions of VM-Entry Controls)", bits_range: (21, 21), - policy: ProfilePolicy::Inherit + policy: ProfilePolicy::Static(0) }, ValueDefinition { short:"ALLOWED_ZERO_LOAD_PKRS", @@ -1333,7 +1335,7 @@ pub static INTEL_MSR_FEATURE_DEFINITIONS: MsrDefinitions<24> = const { short:"ALLOWED_ONE_LOAD_GUEST_IA32_LBR_CTL", description: "See Intel SDM Vol.3C Section 26.8.1 Table 26-17. (Definitions of VM-Entry Controls)", bits_range: (53, 53), - policy: ProfilePolicy::Inherit + policy: ProfilePolicy::Static(0) }, ValueDefinition { short:"ALLOWED_ONE_LOAD_PKRS", @@ -3124,7 +3126,7 @@ pub static INTEL_MSR_FEATURE_DEFINITIONS: MsrDefinitions<24> = const { short:"ALLOWED_ZERO_CLEAR_IA32_LBR_CTL", description: "See Intel SDM Vol.3C Section 26.7.1 Table 26-14 (Definitions of Primary VM-Exit Controls)", bits_range: (26, 26), - policy: ProfilePolicy::Inherit + policy: ProfilePolicy::Static(0) }, ValueDefinition { short:"ALLOWED_ZERO_CLEAR_UINV", @@ -3264,7 +3266,7 @@ pub static INTEL_MSR_FEATURE_DEFINITIONS: MsrDefinitions<24> = const { short:"ALLOWED_ONE_CLEAR_IA32_LBR_CTL", description: "See Intel SDM Vol.3C Section 26.7.1 Table 26-14 (Definitions of Primary VM-Exit Controls)", bits_range: (58, 58), - policy: ProfilePolicy::Inherit + policy: ProfilePolicy::Static(0) }, ValueDefinition { short:"ALLOWED_ONE_CLEAR_UINV", @@ -3396,7 +3398,7 @@ pub static INTEL_MSR_FEATURE_DEFINITIONS: MsrDefinitions<24> = const { short:"ALLOWED_ZERO_LOAD_GUEST_IA32_LBR_CTL", description: "See Intel SDM Vol.3C Section 26.8.1 Table 26-17. (Definitions of VM-Entry Controls)", bits_range: (21, 21), - policy: ProfilePolicy::Inherit + policy: ProfilePolicy::Static(0) }, ValueDefinition { short:"ALLOWED_ZERO_LOAD_PKRS", @@ -3516,7 +3518,7 @@ pub static INTEL_MSR_FEATURE_DEFINITIONS: MsrDefinitions<24> = const { short:"ALLOWED_ONE_LOAD_GUEST_IA32_LBR_CTL", description: "See Intel SDM Vol.3C Section 26.8.1 Table 26-17. (Definitions of VM-Entry Controls)", bits_range: (53, 53), - policy: ProfilePolicy::Inherit + policy: ProfilePolicy::Static(0) }, ValueDefinition { short:"ALLOWED_ONE_LOAD_PKRS",