From 2205d478b90993a259bc94ee1922c2ee06924720 Mon Sep 17 00:00:00 2001 From: stevenfontanella Date: Wed, 28 Jan 2026 19:17:10 +0000 Subject: [PATCH 1/2] Support rmw --- scripts/test/generate-atomic-spec-test.py | 51 +- test/spec/relaxed-atomics.wast | 4079 ++++++++++++++++++++- test/spec/relaxed-atomics2.wast | 331 -- 3 files changed, 4054 insertions(+), 407 deletions(-) delete mode 100644 test/spec/relaxed-atomics2.wast diff --git a/scripts/test/generate-atomic-spec-test.py b/scripts/test/generate-atomic-spec-test.py index 63e64ddbeb0..c67fae9d299 100644 --- a/scripts/test/generate-atomic-spec-test.py +++ b/scripts/test/generate-atomic-spec-test.py @@ -39,8 +39,53 @@ class Template: templates = [ Template(op="i32.atomic.load", value_type=ValueType.i32, args=1, should_drop=True, bin=b"\xfe\x10"), Template(op="i64.atomic.load", value_type=ValueType.i64, args=1, should_drop=True, bin=b"\xfe\x11"), + Template(op="i32.atomic.load8_u", value_type=ValueType.i64, args=1, should_drop=True, bin=b"\xfe\x12"), + Template(op="i32.atomic.load16_u", value_type=ValueType.i64, args=1, should_drop=True, bin=b"\xfe\x13"), + Template(op="i64.atomic.load8_u", value_type=ValueType.i64, args=1, should_drop=True, bin=b"\xfe\x14"), + Template(op="i64.atomic.load16_u", value_type=ValueType.i64, args=1, should_drop=True, bin=b"\xfe\x15"), + Template(op="i64.atomic.load32_u", value_type=ValueType.i64, args=1, should_drop=True, bin=b"\xfe\x16"), Template(op="i32.atomic.store", value_type=ValueType.i32, args=2, should_drop=False, bin=b"\xfe\x17"), Template(op="i64.atomic.store", value_type=ValueType.i64, args=2, should_drop=False, bin=b"\xfe\x18"), + Template(op="i32.atomic.store8", value_type=ValueType.i32, args=2, should_drop=False, bin=b"\xfe\x19"), + Template(op="i32.atomic.store16", value_type=ValueType.i32, args=2, should_drop=False, bin=b"\xfe\x1a"), + Template(op="i64.atomic.store8", value_type=ValueType.i64, args=2, should_drop=False, bin=b"\xfe\x1b"), + Template(op="i64.atomic.store16", value_type=ValueType.i64, args=2, should_drop=False, bin=b"\xfe\x1c"), + Template(op="i64.atomic.store32", value_type=ValueType.i64, args=2, should_drop=False, bin=b"\xfe\x1d"), + Template(op="i32.atomic.rmw.add", value_type=ValueType.i32, args=2, should_drop=True, bin=b"\xfe\x1e"), + Template(op="i64.atomic.rmw.add", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x1f"), + Template(op="i32.atomic.rmw8.add_u", value_type=ValueType.i32, args=2, should_drop=True, bin=b"\xfe\x20"), + Template(op="i32.atomic.rmw16.add_u", value_type=ValueType.i32, args=2, should_drop=True, bin=b"\xfe\x21"), + Template(op="i64.atomic.rmw8.add_u", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x22"), + Template(op="i64.atomic.rmw16.add_u", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x23"), + Template(op="i64.atomic.rmw32.add_u", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x24"), + Template(op="i32.atomic.rmw.sub", value_type=ValueType.i32, args=2, should_drop=True, bin=b"\xfe\x25"), + Template(op="i64.atomic.rmw.sub", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x26"), + Template(op="i32.atomic.rmw8.sub_u", value_type=ValueType.i32, args=2, should_drop=True, bin=b"\xfe\x27"), + Template(op="i32.atomic.rmw16.sub_u", value_type=ValueType.i32, args=2, should_drop=True, bin=b"\xfe\x28"), + Template(op="i64.atomic.rmw8.sub_u", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x29"), + Template(op="i64.atomic.rmw16.sub_u", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x2a"), + Template(op="i64.atomic.rmw32.sub_u", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x2b"), + Template(op="i32.atomic.rmw.and", value_type=ValueType.i32, args=2, should_drop=True, bin=b"\xfe\x2c"), + Template(op="i64.atomic.rmw.and", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x2d"), + Template(op="i32.atomic.rmw8.and_u", value_type=ValueType.i32, args=2, should_drop=True, bin=b"\xfe\x2e"), + Template(op="i32.atomic.rmw16.and_u", value_type=ValueType.i32, args=2, should_drop=True, bin=b"\xfe\x2f"), + Template(op="i64.atomic.rmw8.and_u", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x30"), + Template(op="i64.atomic.rmw16.and_u", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x31"), + Template(op="i64.atomic.rmw32.and_u", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x32"), + Template(op="i32.atomic.rmw.or", value_type=ValueType.i32, args=2, should_drop=True, bin=b"\xfe\x33"), + Template(op="i64.atomic.rmw.or", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x34"), + Template(op="i32.atomic.rmw8.or_u", value_type=ValueType.i32, args=2, should_drop=True, bin=b"\xfe\x35"), + Template(op="i32.atomic.rmw16.or_u", value_type=ValueType.i32, args=2, should_drop=True, bin=b"\xfe\x36"), + Template(op="i64.atomic.rmw8.or_u", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x37"), + Template(op="i64.atomic.rmw16.or_u", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x38"), + Template(op="i64.atomic.rmw32.or_u", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x39"), + Template(op="i32.atomic.rmw.xor", value_type=ValueType.i32, args=2, should_drop=True, bin=b"\xfe\x3a"), + Template(op="i64.atomic.rmw.xor", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x3b"), + Template(op="i32.atomic.rmw8.xor_u", value_type=ValueType.i32, args=2, should_drop=True, bin=b"\xfe\x3c"), + Template(op="i32.atomic.rmw16.xor_u", value_type=ValueType.i32, args=2, should_drop=True, bin=b"\xfe\x3d"), + Template(op="i64.atomic.rmw8.xor_u", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x3e"), + Template(op="i64.atomic.rmw16.xor_u", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x3f"), + Template(op="i64.atomic.rmw32.xor_u", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x40"), ] @@ -151,7 +196,11 @@ def bin_statement_lines(template: Template, mem_idx: int, mem_ptr_type: ValueTyp yield int.to_bytes(mem_idx), "memory index" if has_ordering: - yield int.to_bytes(ordering.value), f"{ordering.name} memory ordering" + ordering_num = ordering.value + if "rmw" in template.op: + ordering_num |= ordering_num << 4 + + yield int.to_bytes(ordering_num), f"{ordering.name} memory ordering" yield b"\x00", "offset" diff --git a/test/spec/relaxed-atomics.wast b/test/spec/relaxed-atomics.wast index c5d7635aa8c..c7d307a90d7 100644 --- a/test/spec/relaxed-atomics.wast +++ b/test/spec/relaxed-atomics.wast @@ -1,92 +1,4021 @@ -;; TODO: replace this with the script generated by scripts/test/generate-atomic-spec-test.py +;; Generated by scripts/test/generate-atomic-spec-test.py. Do not edit manually. (module - (memory 1 1 shared) - (memory 1 1 shared) + (memory i32 1 1) + (memory i64 1 1) - (func $no_ordering_without_memid - (drop (i32.atomic.load (i32.const 51))) - (i32.atomic.store (i32.const 51) (i32.const 51)) - (drop (i32.atomic.rmw.add (i32.const 51) (i32.const 51))) + ;; Memory index must come before memory ordering if present. + ;; Both immediates are optional; an ommitted memory ordering will be treated as seqcst. + (func $test-all-ops + (drop (i32.atomic.load (i32.const 42))) + (drop (i32.atomic.load acqrel (i32.const 42))) + (drop (i32.atomic.load seqcst (i32.const 42))) + (drop (i32.atomic.load 0 (i32.const 42))) + (drop (i32.atomic.load 0 acqrel (i32.const 42))) + (drop (i32.atomic.load 0 seqcst (i32.const 42))) + (drop (i32.atomic.load 1 (i64.const 42))) + (drop (i32.atomic.load 1 acqrel (i64.const 42))) + (drop (i32.atomic.load 1 seqcst (i64.const 42))) + (drop (i64.atomic.load (i32.const 42))) + (drop (i64.atomic.load acqrel (i32.const 42))) + (drop (i64.atomic.load seqcst (i32.const 42))) + (drop (i64.atomic.load 0 (i32.const 42))) + (drop (i64.atomic.load 0 acqrel (i32.const 42))) + (drop (i64.atomic.load 0 seqcst (i32.const 42))) + (drop (i64.atomic.load 1 (i64.const 42))) + (drop (i64.atomic.load 1 acqrel (i64.const 42))) + (drop (i64.atomic.load 1 seqcst (i64.const 42))) + (drop (i32.atomic.load8_u (i32.const 42))) + (drop (i32.atomic.load8_u acqrel (i32.const 42))) + (drop (i32.atomic.load8_u seqcst (i32.const 42))) + (drop (i32.atomic.load8_u 0 (i32.const 42))) + (drop (i32.atomic.load8_u 0 acqrel (i32.const 42))) + (drop (i32.atomic.load8_u 0 seqcst (i32.const 42))) + (drop (i32.atomic.load8_u 1 (i64.const 42))) + (drop (i32.atomic.load8_u 1 acqrel (i64.const 42))) + (drop (i32.atomic.load8_u 1 seqcst (i64.const 42))) + (drop (i32.atomic.load16_u (i32.const 42))) + (drop (i32.atomic.load16_u acqrel (i32.const 42))) + (drop (i32.atomic.load16_u seqcst (i32.const 42))) + (drop (i32.atomic.load16_u 0 (i32.const 42))) + (drop (i32.atomic.load16_u 0 acqrel (i32.const 42))) + (drop (i32.atomic.load16_u 0 seqcst (i32.const 42))) + (drop (i32.atomic.load16_u 1 (i64.const 42))) + (drop (i32.atomic.load16_u 1 acqrel (i64.const 42))) + (drop (i32.atomic.load16_u 1 seqcst (i64.const 42))) + (drop (i64.atomic.load8_u (i32.const 42))) + (drop (i64.atomic.load8_u acqrel (i32.const 42))) + (drop (i64.atomic.load8_u seqcst (i32.const 42))) + (drop (i64.atomic.load8_u 0 (i32.const 42))) + (drop (i64.atomic.load8_u 0 acqrel (i32.const 42))) + (drop (i64.atomic.load8_u 0 seqcst (i32.const 42))) + (drop (i64.atomic.load8_u 1 (i64.const 42))) + (drop (i64.atomic.load8_u 1 acqrel (i64.const 42))) + (drop (i64.atomic.load8_u 1 seqcst (i64.const 42))) + (drop (i64.atomic.load16_u (i32.const 42))) + (drop (i64.atomic.load16_u acqrel (i32.const 42))) + (drop (i64.atomic.load16_u seqcst (i32.const 42))) + (drop (i64.atomic.load16_u 0 (i32.const 42))) + (drop (i64.atomic.load16_u 0 acqrel (i32.const 42))) + (drop (i64.atomic.load16_u 0 seqcst (i32.const 42))) + (drop (i64.atomic.load16_u 1 (i64.const 42))) + (drop (i64.atomic.load16_u 1 acqrel (i64.const 42))) + (drop (i64.atomic.load16_u 1 seqcst (i64.const 42))) + (drop (i64.atomic.load32_u (i32.const 42))) + (drop (i64.atomic.load32_u acqrel (i32.const 42))) + (drop (i64.atomic.load32_u seqcst (i32.const 42))) + (drop (i64.atomic.load32_u 0 (i32.const 42))) + (drop (i64.atomic.load32_u 0 acqrel (i32.const 42))) + (drop (i64.atomic.load32_u 0 seqcst (i32.const 42))) + (drop (i64.atomic.load32_u 1 (i64.const 42))) + (drop (i64.atomic.load32_u 1 acqrel (i64.const 42))) + (drop (i64.atomic.load32_u 1 seqcst (i64.const 42))) + (i32.atomic.store (i32.const 42) (i32.const 42)) + (i32.atomic.store acqrel (i32.const 42) (i32.const 42)) + (i32.atomic.store seqcst (i32.const 42) (i32.const 42)) + (i32.atomic.store 0 (i32.const 42) (i32.const 42)) + (i32.atomic.store 0 acqrel (i32.const 42) (i32.const 42)) + (i32.atomic.store 0 seqcst (i32.const 42) (i32.const 42)) + (i32.atomic.store 1 (i64.const 42) (i32.const 42)) + (i32.atomic.store 1 acqrel (i64.const 42) (i32.const 42)) + (i32.atomic.store 1 seqcst (i64.const 42) (i32.const 42)) + (i64.atomic.store (i32.const 42) (i64.const 42)) + (i64.atomic.store acqrel (i32.const 42) (i64.const 42)) + (i64.atomic.store seqcst (i32.const 42) (i64.const 42)) + (i64.atomic.store 0 (i32.const 42) (i64.const 42)) + (i64.atomic.store 0 acqrel (i32.const 42) (i64.const 42)) + (i64.atomic.store 0 seqcst (i32.const 42) (i64.const 42)) + (i64.atomic.store 1 (i64.const 42) (i64.const 42)) + (i64.atomic.store 1 acqrel (i64.const 42) (i64.const 42)) + (i64.atomic.store 1 seqcst (i64.const 42) (i64.const 42)) + (i32.atomic.store8 (i32.const 42) (i32.const 42)) + (i32.atomic.store8 acqrel (i32.const 42) (i32.const 42)) + (i32.atomic.store8 seqcst (i32.const 42) (i32.const 42)) + (i32.atomic.store8 0 (i32.const 42) (i32.const 42)) + (i32.atomic.store8 0 acqrel (i32.const 42) (i32.const 42)) + (i32.atomic.store8 0 seqcst (i32.const 42) (i32.const 42)) + (i32.atomic.store8 1 (i64.const 42) (i32.const 42)) + (i32.atomic.store8 1 acqrel (i64.const 42) (i32.const 42)) + (i32.atomic.store8 1 seqcst (i64.const 42) (i32.const 42)) + (i32.atomic.store16 (i32.const 42) (i32.const 42)) + (i32.atomic.store16 acqrel (i32.const 42) (i32.const 42)) + (i32.atomic.store16 seqcst (i32.const 42) (i32.const 42)) + (i32.atomic.store16 0 (i32.const 42) (i32.const 42)) + (i32.atomic.store16 0 acqrel (i32.const 42) (i32.const 42)) + (i32.atomic.store16 0 seqcst (i32.const 42) (i32.const 42)) + (i32.atomic.store16 1 (i64.const 42) (i32.const 42)) + (i32.atomic.store16 1 acqrel (i64.const 42) (i32.const 42)) + (i32.atomic.store16 1 seqcst (i64.const 42) (i32.const 42)) + (i64.atomic.store8 (i32.const 42) (i64.const 42)) + (i64.atomic.store8 acqrel (i32.const 42) (i64.const 42)) + (i64.atomic.store8 seqcst (i32.const 42) (i64.const 42)) + (i64.atomic.store8 0 (i32.const 42) (i64.const 42)) + (i64.atomic.store8 0 acqrel (i32.const 42) (i64.const 42)) + (i64.atomic.store8 0 seqcst (i32.const 42) (i64.const 42)) + (i64.atomic.store8 1 (i64.const 42) (i64.const 42)) + (i64.atomic.store8 1 acqrel (i64.const 42) (i64.const 42)) + (i64.atomic.store8 1 seqcst (i64.const 42) (i64.const 42)) + (i64.atomic.store16 (i32.const 42) (i64.const 42)) + (i64.atomic.store16 acqrel (i32.const 42) (i64.const 42)) + (i64.atomic.store16 seqcst (i32.const 42) (i64.const 42)) + (i64.atomic.store16 0 (i32.const 42) (i64.const 42)) + (i64.atomic.store16 0 acqrel (i32.const 42) (i64.const 42)) + (i64.atomic.store16 0 seqcst (i32.const 42) (i64.const 42)) + (i64.atomic.store16 1 (i64.const 42) (i64.const 42)) + (i64.atomic.store16 1 acqrel (i64.const 42) (i64.const 42)) + (i64.atomic.store16 1 seqcst (i64.const 42) (i64.const 42)) + (i64.atomic.store32 (i32.const 42) (i64.const 42)) + (i64.atomic.store32 acqrel (i32.const 42) (i64.const 42)) + (i64.atomic.store32 seqcst (i32.const 42) (i64.const 42)) + (i64.atomic.store32 0 (i32.const 42) (i64.const 42)) + (i64.atomic.store32 0 acqrel (i32.const 42) (i64.const 42)) + (i64.atomic.store32 0 seqcst (i32.const 42) (i64.const 42)) + (i64.atomic.store32 1 (i64.const 42) (i64.const 42)) + (i64.atomic.store32 1 acqrel (i64.const 42) (i64.const 42)) + (i64.atomic.store32 1 seqcst (i64.const 42) (i64.const 42)) + (drop (i32.atomic.rmw.add (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.add acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.add seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.add 0 (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.add 0 acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.add 0 seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.add 1 (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.add 1 acqrel (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.add 1 seqcst (i64.const 42) (i32.const 42))) + (drop (i64.atomic.rmw.add (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.add acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.add seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.add 0 (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.add 0 acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.add 0 seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.add 1 (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.add 1 acqrel (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.add 1 seqcst (i64.const 42) (i64.const 42))) + (drop (i32.atomic.rmw8.add_u (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.add_u acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.add_u seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.add_u 0 (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.add_u 0 acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.add_u 0 seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.add_u 1 (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.add_u 1 acqrel (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.add_u 1 seqcst (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.add_u (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.add_u acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.add_u seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.add_u 0 (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.add_u 0 acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.add_u 0 seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.add_u 1 (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.add_u 1 acqrel (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.add_u 1 seqcst (i64.const 42) (i32.const 42))) + (drop (i64.atomic.rmw8.add_u (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.add_u acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.add_u seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.add_u 0 (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.add_u 0 acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.add_u 0 seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.add_u 1 (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.add_u 1 acqrel (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.add_u 1 seqcst (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.add_u (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.add_u acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.add_u seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.add_u 0 (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.add_u 0 acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.add_u 0 seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.add_u 1 (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.add_u 1 acqrel (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.add_u 1 seqcst (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.add_u (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.add_u acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.add_u seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.add_u 0 (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.add_u 0 acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.add_u 0 seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.add_u 1 (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.add_u 1 acqrel (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.add_u 1 seqcst (i64.const 42) (i64.const 42))) + (drop (i32.atomic.rmw.sub (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.sub acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.sub seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.sub 0 (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.sub 0 acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.sub 0 seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.sub 1 (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.sub 1 acqrel (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.sub 1 seqcst (i64.const 42) (i32.const 42))) + (drop (i64.atomic.rmw.sub (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.sub acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.sub seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.sub 0 (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.sub 0 acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.sub 0 seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.sub 1 (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.sub 1 acqrel (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.sub 1 seqcst (i64.const 42) (i64.const 42))) + (drop (i32.atomic.rmw8.sub_u (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.sub_u acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.sub_u seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.sub_u 0 (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.sub_u 0 acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.sub_u 0 seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.sub_u 1 (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.sub_u 1 acqrel (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.sub_u 1 seqcst (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.sub_u (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.sub_u acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.sub_u seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.sub_u 0 (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.sub_u 0 acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.sub_u 0 seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.sub_u 1 (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.sub_u 1 acqrel (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.sub_u 1 seqcst (i64.const 42) (i32.const 42))) + (drop (i64.atomic.rmw8.sub_u (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.sub_u acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.sub_u seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.sub_u 0 (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.sub_u 0 acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.sub_u 0 seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.sub_u 1 (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.sub_u 1 acqrel (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.sub_u 1 seqcst (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.sub_u (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.sub_u acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.sub_u seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.sub_u 0 (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.sub_u 0 acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.sub_u 0 seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.sub_u 1 (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.sub_u 1 acqrel (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.sub_u 1 seqcst (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.sub_u (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.sub_u acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.sub_u seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.sub_u 0 (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.sub_u 0 acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.sub_u 0 seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.sub_u 1 (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.sub_u 1 acqrel (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.sub_u 1 seqcst (i64.const 42) (i64.const 42))) + (drop (i32.atomic.rmw.and (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.and acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.and seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.and 0 (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.and 0 acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.and 0 seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.and 1 (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.and 1 acqrel (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.and 1 seqcst (i64.const 42) (i32.const 42))) + (drop (i64.atomic.rmw.and (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.and acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.and seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.and 0 (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.and 0 acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.and 0 seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.and 1 (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.and 1 acqrel (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.and 1 seqcst (i64.const 42) (i64.const 42))) + (drop (i32.atomic.rmw8.and_u (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.and_u acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.and_u seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.and_u 0 (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.and_u 0 acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.and_u 0 seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.and_u 1 (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.and_u 1 acqrel (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.and_u 1 seqcst (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.and_u (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.and_u acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.and_u seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.and_u 0 (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.and_u 0 acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.and_u 0 seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.and_u 1 (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.and_u 1 acqrel (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.and_u 1 seqcst (i64.const 42) (i32.const 42))) + (drop (i64.atomic.rmw8.and_u (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.and_u acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.and_u seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.and_u 0 (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.and_u 0 acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.and_u 0 seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.and_u 1 (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.and_u 1 acqrel (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.and_u 1 seqcst (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.and_u (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.and_u acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.and_u seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.and_u 0 (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.and_u 0 acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.and_u 0 seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.and_u 1 (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.and_u 1 acqrel (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.and_u 1 seqcst (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.and_u (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.and_u acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.and_u seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.and_u 0 (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.and_u 0 acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.and_u 0 seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.and_u 1 (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.and_u 1 acqrel (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.and_u 1 seqcst (i64.const 42) (i64.const 42))) + (drop (i32.atomic.rmw.or (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.or acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.or seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.or 0 (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.or 0 acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.or 0 seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.or 1 (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.or 1 acqrel (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.or 1 seqcst (i64.const 42) (i32.const 42))) + (drop (i64.atomic.rmw.or (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.or acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.or seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.or 0 (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.or 0 acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.or 0 seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.or 1 (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.or 1 acqrel (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.or 1 seqcst (i64.const 42) (i64.const 42))) + (drop (i32.atomic.rmw8.or_u (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.or_u acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.or_u seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.or_u 0 (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.or_u 0 acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.or_u 0 seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.or_u 1 (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.or_u 1 acqrel (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.or_u 1 seqcst (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.or_u (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.or_u acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.or_u seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.or_u 0 (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.or_u 0 acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.or_u 0 seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.or_u 1 (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.or_u 1 acqrel (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.or_u 1 seqcst (i64.const 42) (i32.const 42))) + (drop (i64.atomic.rmw8.or_u (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.or_u acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.or_u seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.or_u 0 (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.or_u 0 acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.or_u 0 seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.or_u 1 (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.or_u 1 acqrel (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.or_u 1 seqcst (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.or_u (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.or_u acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.or_u seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.or_u 0 (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.or_u 0 acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.or_u 0 seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.or_u 1 (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.or_u 1 acqrel (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.or_u 1 seqcst (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.or_u (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.or_u acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.or_u seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.or_u 0 (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.or_u 0 acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.or_u 0 seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.or_u 1 (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.or_u 1 acqrel (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.or_u 1 seqcst (i64.const 42) (i64.const 42))) + (drop (i32.atomic.rmw.xor (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.xor acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.xor seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.xor 0 (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.xor 0 acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.xor 0 seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.xor 1 (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.xor 1 acqrel (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.xor 1 seqcst (i64.const 42) (i32.const 42))) + (drop (i64.atomic.rmw.xor (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.xor acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.xor seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.xor 0 (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.xor 0 acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.xor 0 seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.xor 1 (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.xor 1 acqrel (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.xor 1 seqcst (i64.const 42) (i64.const 42))) + (drop (i32.atomic.rmw8.xor_u (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.xor_u acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.xor_u seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.xor_u 0 (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.xor_u 0 acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.xor_u 0 seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.xor_u 1 (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.xor_u 1 acqrel (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.xor_u 1 seqcst (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.xor_u (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.xor_u acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.xor_u seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.xor_u 0 (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.xor_u 0 acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.xor_u 0 seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.xor_u 1 (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.xor_u 1 acqrel (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.xor_u 1 seqcst (i64.const 42) (i32.const 42))) + (drop (i64.atomic.rmw8.xor_u (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.xor_u acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.xor_u seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.xor_u 0 (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.xor_u 0 acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.xor_u 0 seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.xor_u 1 (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.xor_u 1 acqrel (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.xor_u 1 seqcst (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.xor_u (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.xor_u acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.xor_u seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.xor_u 0 (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.xor_u 0 acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.xor_u 0 seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.xor_u 1 (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.xor_u 1 acqrel (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.xor_u 1 seqcst (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.xor_u (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.xor_u acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.xor_u seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.xor_u 0 (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.xor_u 0 acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.xor_u 0 seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.xor_u 1 (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.xor_u 1 acqrel (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.xor_u 1 seqcst (i64.const 42) (i64.const 42))) ) +) - (func $acqrel_without_memid - (drop (i32.atomic.load acqrel (i32.const 51))) - (i32.atomic.store acqrel (i32.const 51) (i32.const 51)) - (drop (i32.atomic.rmw.add acqrel (i32.const 51) (i32.const 51))) - ) +(assert_invalid (module + (memory 1 1 shared) - (func $seqcst_without_memid - (drop (i32.atomic.load seqcst (i32.const 51))) - (i32.atomic.store seqcst (i32.const 51) (i32.const 51)) - (drop (i32.atomic.rmw.add seqcst (i32.const 51) (i32.const 51))) - ) + (func $i32load (drop (i32.load acqrel (i32.const 51)))) +) "Can't set memory ordering for non-atomic i32.load") - (func $no_ordering_with_memid - (drop (i32.atomic.load 1 (i32.const 51))) - (i32.atomic.store 1 (i32.const 51) (i32.const 51)) - (drop (i32.atomic.rmw.add 1 (i32.const 51) (i32.const 51))) - ) +(module binary + "\00asm\01\00\00\00" ;; Wasm header + "\01\04\01" ;; Type section + "\60\00\00" ;; $test-all-ops type + "\03\02\01\00" ;; Function section + "\05\07\02" ;; Memory section + "\01\01\01" ;; (memory i32 1 1) + "\05\01\01" ;; (memory i64 1 1) + "\0a\95\22\01" ;; Code section + "\92\22\00" ;; func $test-all-ops - (func $acqrel_with_memid - (drop (i32.atomic.load 1 acqrel (i32.const 51))) - (i32.atomic.store 1 acqrel (i32.const 51) (i32.const 51)) - (drop (i32.atomic.rmw.add 1 acqrel (i32.const 51) (i32.const 51))) - ) + "\41\33" ;; (i32.const 51) + "\fe\10" ;; i32.atomic.load + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop - (func $seqcst_with_memid - (drop (i32.atomic.load 1 seqcst (i32.const 51))) - (i32.atomic.store 1 seqcst (i32.const 51) (i32.const 51)) - (drop (i32.atomic.rmw.add 1 seqcst (i32.const 51) (i32.const 51))) - ) -) + "\41\33" ;; (i32.const 51) + "\fe\10" ;; i32.atomic.load + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\01" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop -(module binary - "\00asm\01\00\00\00" ;; header + version - "\01\05\01\60\00\01\7f\03\02\01\00\05\05\01\03\17\80\02" ;; other sections - "\0a\0c\01" ;; code section - "\0a\00" ;; func size + decl count - "\41\33" ;; i32.const 51 + "\41\33" ;; (i32.const 51) + "\fe\10" ;; i32.atomic.load + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) "\fe\10" ;; i32.atomic.load - "\62" ;; 2 | (1<<5) | (1<<6): Alignment of 2 (32-bit load), with bit 5 set indicating that the next byte is a memory ordering + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows "\00" ;; memory index - "\01" ;; acqrel ordering "\00" ;; offset - "\0b" ;; end -) + "\1a" ;; drop -(module binary - "\00\61\73\6d\01\00\00\00\01\04\01\60\00\00\03\07\06\00\00\00\00\00\00\05\07\02\03\01\01\03\01\01" - "\0a\b8\01\06" ;; code section - "\1a\00" ;; func - "\41\33\fe\10\02\00\1a" ;; (drop (i32.atomic.load (i32.const 51))) - "\41\33\41\33\fe\17\02\00" ;; (i32.atomic.store (i32.const 51) (i32.const 51)) - "\41\33\41\33\fe\1e\02\00\1a\0b" ;; (drop (i32.atomic.rmw.add (i32.const 51) (i32.const 51))) - "\1d\00" ;; func - "\41\33\fe\10\22\00\00\1a" ;; (drop (i32.atomic.load seqcst (i32.const 51))) - "\41\33\41\33\fe\17\22\00\00" ;; (i32.atomic.store seqcst (i32.const 51) (i32.const 51)) - "\41\33\41\33\fe\1e\22\00\00\1a\0b" ;; (drop (i32.atomic.rmw.add seqcst (i32.const 51) (i32.const 51))) - "\1d\00" ;; func - "\41\33\fe\10\22\01\00\1a" ;; (drop (i32.atomic.load acqrel (i32.const 51))) - "\41\33\41\33\fe\17\22\01\00" ;; (i32.atomic.store acqrel (i32.const 51) (i32.const 51)) - "\41\33\41\33\fe\1e\22\11\00\1a\0b" ;; (drop (i32.atomic.rmw.add acqrel (i32.const 51) (i32.const 51))) - "\1d\00" ;; func - "\41\33\fe\10\42\01\00\1a" ;; (drop (i32.atomic.load 1 (i32.const 51))) - "\41\33\41\33\fe\17\42\01\00" ;; (i32.atomic.store 1 (i32.const 51) (i32.const 51)) - "\41\33\41\33\fe\1e\42\01\00\1a\0b" ;; (drop (i32.atomic.rmw.add 1 (i32.const 51) (i32.const 51))) - "\20\00" ;; func - "\41\33\fe\10\62\01\00\00\1a" ;; (drop (i32.atomic.load 1 seqcst (i32.const 51))) - "\41\33\41\33\fe\17\62\01\00\00" ;; (i32.atomic.store 1 seqcst (i32.const 51) (i32.const 51)) - "\41\33\41\33\fe\1e\62\01\00\00\1a\0b" ;; (drop (i32.atomic.rmw.add 1 seqcst (i32.const 51) (i32.const 51))) - "\20\00" ;; func - "\41\33\fe\10\62\01\01\00\1a" ;; (drop (i32.atomic.load 1 acqrel (i32.const 51))) - "\41\33\41\33\fe\17\62\01\01\00" ;; (i32.atomic.store 1 acqrel (i32.const 51) (i32.const 51)) - "\41\33\41\33\fe\1e\62\01\11\00\1a\0b" ;; (drop (i32.atomic.rmw.add 1 acqrel (i32.const 51) (i32.const 51))) -) + "\41\33" ;; (i32.const 51) + "\fe\10" ;; i32.atomic.load + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop -(assert_invalid (module - (memory 1 1 shared) + "\41\33" ;; (i32.const 51) + "\fe\10" ;; i32.atomic.load + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop - (func $i32load (drop (i32.load acqrel (i32.const 51)))) -) "Can't set memory ordering for non-atomic i32.load") + "\42\33" ;; (i64.const 51) + "\fe\10" ;; i32.atomic.load + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\fe\10" ;; i32.atomic.load + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\fe\10" ;; i32.atomic.load + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\11" ;; i64.atomic.load + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\11" ;; i64.atomic.load + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\01" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\11" ;; i64.atomic.load + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\11" ;; i64.atomic.load + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\11" ;; i64.atomic.load + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\11" ;; i64.atomic.load + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\fe\11" ;; i64.atomic.load + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\fe\11" ;; i64.atomic.load + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\fe\11" ;; i64.atomic.load + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\12" ;; i32.atomic.load8_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\12" ;; i32.atomic.load8_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\01" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\12" ;; i32.atomic.load8_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\12" ;; i32.atomic.load8_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\12" ;; i32.atomic.load8_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\12" ;; i32.atomic.load8_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\fe\12" ;; i32.atomic.load8_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\fe\12" ;; i32.atomic.load8_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\fe\12" ;; i32.atomic.load8_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\13" ;; i32.atomic.load16_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\13" ;; i32.atomic.load16_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\01" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\13" ;; i32.atomic.load16_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\13" ;; i32.atomic.load16_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\13" ;; i32.atomic.load16_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\13" ;; i32.atomic.load16_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\fe\13" ;; i32.atomic.load16_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\fe\13" ;; i32.atomic.load16_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\fe\13" ;; i32.atomic.load16_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\14" ;; i64.atomic.load8_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\14" ;; i64.atomic.load8_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\01" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\14" ;; i64.atomic.load8_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\14" ;; i64.atomic.load8_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\14" ;; i64.atomic.load8_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\14" ;; i64.atomic.load8_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\fe\14" ;; i64.atomic.load8_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\fe\14" ;; i64.atomic.load8_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\fe\14" ;; i64.atomic.load8_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\15" ;; i64.atomic.load16_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\15" ;; i64.atomic.load16_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\01" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\15" ;; i64.atomic.load16_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\15" ;; i64.atomic.load16_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\15" ;; i64.atomic.load16_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\15" ;; i64.atomic.load16_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\fe\15" ;; i64.atomic.load16_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\fe\15" ;; i64.atomic.load16_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\fe\15" ;; i64.atomic.load16_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\16" ;; i64.atomic.load32_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\16" ;; i64.atomic.load32_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\01" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\16" ;; i64.atomic.load32_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\16" ;; i64.atomic.load32_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\16" ;; i64.atomic.load32_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\fe\16" ;; i64.atomic.load32_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\fe\16" ;; i64.atomic.load32_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\fe\16" ;; i64.atomic.load32_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\fe\16" ;; i64.atomic.load32_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\17" ;; i32.atomic.store + "\02" ;; Alignment of 2 + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\17" ;; i32.atomic.store + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\01" ;; acqrel memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\17" ;; i32.atomic.store + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\17" ;; i32.atomic.store + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\17" ;; i32.atomic.store + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\17" ;; i32.atomic.store + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\17" ;; i32.atomic.store + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\17" ;; i32.atomic.store + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\17" ;; i32.atomic.store + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\18" ;; i64.atomic.store + "\02" ;; Alignment of 2 + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\18" ;; i64.atomic.store + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\01" ;; acqrel memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\18" ;; i64.atomic.store + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\18" ;; i64.atomic.store + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\18" ;; i64.atomic.store + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\18" ;; i64.atomic.store + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\18" ;; i64.atomic.store + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\18" ;; i64.atomic.store + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\18" ;; i64.atomic.store + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\19" ;; i32.atomic.store8 + "\02" ;; Alignment of 2 + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\19" ;; i32.atomic.store8 + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\01" ;; acqrel memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\19" ;; i32.atomic.store8 + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\19" ;; i32.atomic.store8 + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\19" ;; i32.atomic.store8 + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\19" ;; i32.atomic.store8 + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\19" ;; i32.atomic.store8 + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\19" ;; i32.atomic.store8 + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\19" ;; i32.atomic.store8 + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\1a" ;; i32.atomic.store16 + "\02" ;; Alignment of 2 + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\1a" ;; i32.atomic.store16 + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\01" ;; acqrel memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\1a" ;; i32.atomic.store16 + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\1a" ;; i32.atomic.store16 + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\1a" ;; i32.atomic.store16 + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\1a" ;; i32.atomic.store16 + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\1a" ;; i32.atomic.store16 + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\1a" ;; i32.atomic.store16 + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\1a" ;; i32.atomic.store16 + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1b" ;; i64.atomic.store8 + "\02" ;; Alignment of 2 + "\00" ;; offset + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1b" ;; i64.atomic.store8 + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\01" ;; acqrel memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1b" ;; i64.atomic.store8 + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1b" ;; i64.atomic.store8 + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1b" ;; i64.atomic.store8 + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1b" ;; i64.atomic.store8 + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1b" ;; i64.atomic.store8 + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1b" ;; i64.atomic.store8 + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1b" ;; i64.atomic.store8 + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1c" ;; i64.atomic.store16 + "\02" ;; Alignment of 2 + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1c" ;; i64.atomic.store16 + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\01" ;; acqrel memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1c" ;; i64.atomic.store16 + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1c" ;; i64.atomic.store16 + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1c" ;; i64.atomic.store16 + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1c" ;; i64.atomic.store16 + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1c" ;; i64.atomic.store16 + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1c" ;; i64.atomic.store16 + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1c" ;; i64.atomic.store16 + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1d" ;; i64.atomic.store32 + "\02" ;; Alignment of 2 + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1d" ;; i64.atomic.store32 + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\01" ;; acqrel memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1d" ;; i64.atomic.store32 + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1d" ;; i64.atomic.store32 + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1d" ;; i64.atomic.store32 + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1d" ;; i64.atomic.store32 + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1d" ;; i64.atomic.store32 + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1d" ;; i64.atomic.store32 + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\01" ;; acqrel memory ordering + "\00" ;; offset + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1d" ;; i64.atomic.store32 + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\1e" ;; i32.atomic.rmw.add + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\1e" ;; i32.atomic.rmw.add + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\1e" ;; i32.atomic.rmw.add + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\1e" ;; i32.atomic.rmw.add + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\1e" ;; i32.atomic.rmw.add + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\1e" ;; i32.atomic.rmw.add + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\1e" ;; i32.atomic.rmw.add + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\1e" ;; i32.atomic.rmw.add + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\1e" ;; i32.atomic.rmw.add + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1f" ;; i64.atomic.rmw.add + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1f" ;; i64.atomic.rmw.add + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1f" ;; i64.atomic.rmw.add + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1f" ;; i64.atomic.rmw.add + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1f" ;; i64.atomic.rmw.add + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1f" ;; i64.atomic.rmw.add + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1f" ;; i64.atomic.rmw.add + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1f" ;; i64.atomic.rmw.add + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\1f" ;; i64.atomic.rmw.add + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\20" ;; i32.atomic.rmw8.add_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\20" ;; i32.atomic.rmw8.add_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\20" ;; i32.atomic.rmw8.add_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\20" ;; i32.atomic.rmw8.add_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\20" ;; i32.atomic.rmw8.add_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\20" ;; i32.atomic.rmw8.add_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\20" ;; i32.atomic.rmw8.add_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\20" ;; i32.atomic.rmw8.add_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\20" ;; i32.atomic.rmw8.add_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\21" ;; i32.atomic.rmw16.add_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\21" ;; i32.atomic.rmw16.add_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\21" ;; i32.atomic.rmw16.add_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\21" ;; i32.atomic.rmw16.add_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\21" ;; i32.atomic.rmw16.add_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\21" ;; i32.atomic.rmw16.add_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\21" ;; i32.atomic.rmw16.add_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\21" ;; i32.atomic.rmw16.add_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\21" ;; i32.atomic.rmw16.add_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\22" ;; i64.atomic.rmw8.add_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\22" ;; i64.atomic.rmw8.add_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\22" ;; i64.atomic.rmw8.add_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\22" ;; i64.atomic.rmw8.add_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\22" ;; i64.atomic.rmw8.add_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\22" ;; i64.atomic.rmw8.add_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\22" ;; i64.atomic.rmw8.add_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\22" ;; i64.atomic.rmw8.add_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\22" ;; i64.atomic.rmw8.add_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\23" ;; i64.atomic.rmw16.add_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\23" ;; i64.atomic.rmw16.add_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\23" ;; i64.atomic.rmw16.add_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\23" ;; i64.atomic.rmw16.add_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\23" ;; i64.atomic.rmw16.add_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\23" ;; i64.atomic.rmw16.add_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\23" ;; i64.atomic.rmw16.add_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\23" ;; i64.atomic.rmw16.add_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\23" ;; i64.atomic.rmw16.add_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\24" ;; i64.atomic.rmw32.add_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\24" ;; i64.atomic.rmw32.add_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\24" ;; i64.atomic.rmw32.add_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\24" ;; i64.atomic.rmw32.add_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\24" ;; i64.atomic.rmw32.add_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\24" ;; i64.atomic.rmw32.add_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\24" ;; i64.atomic.rmw32.add_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\24" ;; i64.atomic.rmw32.add_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\24" ;; i64.atomic.rmw32.add_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\25" ;; i32.atomic.rmw.sub + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\25" ;; i32.atomic.rmw.sub + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\25" ;; i32.atomic.rmw.sub + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\25" ;; i32.atomic.rmw.sub + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\25" ;; i32.atomic.rmw.sub + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\25" ;; i32.atomic.rmw.sub + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\25" ;; i32.atomic.rmw.sub + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\25" ;; i32.atomic.rmw.sub + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\25" ;; i32.atomic.rmw.sub + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\26" ;; i64.atomic.rmw.sub + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\26" ;; i64.atomic.rmw.sub + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\26" ;; i64.atomic.rmw.sub + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\26" ;; i64.atomic.rmw.sub + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\26" ;; i64.atomic.rmw.sub + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\26" ;; i64.atomic.rmw.sub + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\26" ;; i64.atomic.rmw.sub + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\26" ;; i64.atomic.rmw.sub + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\26" ;; i64.atomic.rmw.sub + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\27" ;; i32.atomic.rmw8.sub_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\27" ;; i32.atomic.rmw8.sub_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\27" ;; i32.atomic.rmw8.sub_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\27" ;; i32.atomic.rmw8.sub_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\27" ;; i32.atomic.rmw8.sub_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\27" ;; i32.atomic.rmw8.sub_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\27" ;; i32.atomic.rmw8.sub_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\27" ;; i32.atomic.rmw8.sub_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\27" ;; i32.atomic.rmw8.sub_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\28" ;; i32.atomic.rmw16.sub_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\28" ;; i32.atomic.rmw16.sub_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\28" ;; i32.atomic.rmw16.sub_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\28" ;; i32.atomic.rmw16.sub_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\28" ;; i32.atomic.rmw16.sub_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\28" ;; i32.atomic.rmw16.sub_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\28" ;; i32.atomic.rmw16.sub_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\28" ;; i32.atomic.rmw16.sub_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\28" ;; i32.atomic.rmw16.sub_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\29" ;; i64.atomic.rmw8.sub_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\29" ;; i64.atomic.rmw8.sub_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\29" ;; i64.atomic.rmw8.sub_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\29" ;; i64.atomic.rmw8.sub_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\29" ;; i64.atomic.rmw8.sub_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\29" ;; i64.atomic.rmw8.sub_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\29" ;; i64.atomic.rmw8.sub_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\29" ;; i64.atomic.rmw8.sub_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\29" ;; i64.atomic.rmw8.sub_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2a" ;; i64.atomic.rmw16.sub_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2a" ;; i64.atomic.rmw16.sub_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2a" ;; i64.atomic.rmw16.sub_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2a" ;; i64.atomic.rmw16.sub_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2a" ;; i64.atomic.rmw16.sub_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2a" ;; i64.atomic.rmw16.sub_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2a" ;; i64.atomic.rmw16.sub_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2a" ;; i64.atomic.rmw16.sub_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2a" ;; i64.atomic.rmw16.sub_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2b" ;; i64.atomic.rmw32.sub_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2b" ;; i64.atomic.rmw32.sub_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2b" ;; i64.atomic.rmw32.sub_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2b" ;; i64.atomic.rmw32.sub_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2b" ;; i64.atomic.rmw32.sub_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2b" ;; i64.atomic.rmw32.sub_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2b" ;; i64.atomic.rmw32.sub_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2b" ;; i64.atomic.rmw32.sub_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2b" ;; i64.atomic.rmw32.sub_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2c" ;; i32.atomic.rmw.and + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2c" ;; i32.atomic.rmw.and + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2c" ;; i32.atomic.rmw.and + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2c" ;; i32.atomic.rmw.and + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2c" ;; i32.atomic.rmw.and + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2c" ;; i32.atomic.rmw.and + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2c" ;; i32.atomic.rmw.and + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2c" ;; i32.atomic.rmw.and + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2c" ;; i32.atomic.rmw.and + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2d" ;; i64.atomic.rmw.and + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2d" ;; i64.atomic.rmw.and + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2d" ;; i64.atomic.rmw.and + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2d" ;; i64.atomic.rmw.and + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2d" ;; i64.atomic.rmw.and + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2d" ;; i64.atomic.rmw.and + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2d" ;; i64.atomic.rmw.and + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2d" ;; i64.atomic.rmw.and + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\2d" ;; i64.atomic.rmw.and + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2e" ;; i32.atomic.rmw8.and_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2e" ;; i32.atomic.rmw8.and_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2e" ;; i32.atomic.rmw8.and_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2e" ;; i32.atomic.rmw8.and_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2e" ;; i32.atomic.rmw8.and_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2e" ;; i32.atomic.rmw8.and_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2e" ;; i32.atomic.rmw8.and_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2e" ;; i32.atomic.rmw8.and_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2e" ;; i32.atomic.rmw8.and_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2f" ;; i32.atomic.rmw16.and_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2f" ;; i32.atomic.rmw16.and_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2f" ;; i32.atomic.rmw16.and_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2f" ;; i32.atomic.rmw16.and_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2f" ;; i32.atomic.rmw16.and_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2f" ;; i32.atomic.rmw16.and_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2f" ;; i32.atomic.rmw16.and_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2f" ;; i32.atomic.rmw16.and_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\2f" ;; i32.atomic.rmw16.and_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\30" ;; i64.atomic.rmw8.and_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\30" ;; i64.atomic.rmw8.and_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\30" ;; i64.atomic.rmw8.and_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\30" ;; i64.atomic.rmw8.and_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\30" ;; i64.atomic.rmw8.and_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\30" ;; i64.atomic.rmw8.and_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\30" ;; i64.atomic.rmw8.and_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\30" ;; i64.atomic.rmw8.and_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\30" ;; i64.atomic.rmw8.and_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\31" ;; i64.atomic.rmw16.and_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\31" ;; i64.atomic.rmw16.and_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\31" ;; i64.atomic.rmw16.and_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\31" ;; i64.atomic.rmw16.and_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\31" ;; i64.atomic.rmw16.and_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\31" ;; i64.atomic.rmw16.and_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\31" ;; i64.atomic.rmw16.and_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\31" ;; i64.atomic.rmw16.and_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\31" ;; i64.atomic.rmw16.and_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\32" ;; i64.atomic.rmw32.and_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\32" ;; i64.atomic.rmw32.and_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\32" ;; i64.atomic.rmw32.and_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\32" ;; i64.atomic.rmw32.and_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\32" ;; i64.atomic.rmw32.and_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\32" ;; i64.atomic.rmw32.and_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\32" ;; i64.atomic.rmw32.and_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\32" ;; i64.atomic.rmw32.and_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\32" ;; i64.atomic.rmw32.and_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\33" ;; i32.atomic.rmw.or + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\33" ;; i32.atomic.rmw.or + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\33" ;; i32.atomic.rmw.or + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\33" ;; i32.atomic.rmw.or + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\33" ;; i32.atomic.rmw.or + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\33" ;; i32.atomic.rmw.or + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\33" ;; i32.atomic.rmw.or + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\33" ;; i32.atomic.rmw.or + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\33" ;; i32.atomic.rmw.or + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\34" ;; i64.atomic.rmw.or + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\34" ;; i64.atomic.rmw.or + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\34" ;; i64.atomic.rmw.or + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\34" ;; i64.atomic.rmw.or + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\34" ;; i64.atomic.rmw.or + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\34" ;; i64.atomic.rmw.or + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\34" ;; i64.atomic.rmw.or + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\34" ;; i64.atomic.rmw.or + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\34" ;; i64.atomic.rmw.or + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\35" ;; i32.atomic.rmw8.or_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\35" ;; i32.atomic.rmw8.or_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\35" ;; i32.atomic.rmw8.or_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\35" ;; i32.atomic.rmw8.or_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\35" ;; i32.atomic.rmw8.or_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\35" ;; i32.atomic.rmw8.or_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\35" ;; i32.atomic.rmw8.or_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\35" ;; i32.atomic.rmw8.or_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\35" ;; i32.atomic.rmw8.or_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\36" ;; i32.atomic.rmw16.or_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\36" ;; i32.atomic.rmw16.or_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\36" ;; i32.atomic.rmw16.or_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\36" ;; i32.atomic.rmw16.or_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\36" ;; i32.atomic.rmw16.or_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\36" ;; i32.atomic.rmw16.or_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\36" ;; i32.atomic.rmw16.or_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\36" ;; i32.atomic.rmw16.or_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\36" ;; i32.atomic.rmw16.or_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\37" ;; i64.atomic.rmw8.or_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\37" ;; i64.atomic.rmw8.or_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\37" ;; i64.atomic.rmw8.or_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\37" ;; i64.atomic.rmw8.or_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\37" ;; i64.atomic.rmw8.or_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\37" ;; i64.atomic.rmw8.or_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\37" ;; i64.atomic.rmw8.or_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\37" ;; i64.atomic.rmw8.or_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\37" ;; i64.atomic.rmw8.or_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\38" ;; i64.atomic.rmw16.or_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\38" ;; i64.atomic.rmw16.or_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\38" ;; i64.atomic.rmw16.or_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\38" ;; i64.atomic.rmw16.or_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\38" ;; i64.atomic.rmw16.or_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\38" ;; i64.atomic.rmw16.or_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\38" ;; i64.atomic.rmw16.or_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\38" ;; i64.atomic.rmw16.or_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\38" ;; i64.atomic.rmw16.or_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\39" ;; i64.atomic.rmw32.or_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\39" ;; i64.atomic.rmw32.or_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\39" ;; i64.atomic.rmw32.or_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\39" ;; i64.atomic.rmw32.or_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\39" ;; i64.atomic.rmw32.or_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\39" ;; i64.atomic.rmw32.or_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\39" ;; i64.atomic.rmw32.or_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\39" ;; i64.atomic.rmw32.or_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\39" ;; i64.atomic.rmw32.or_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3a" ;; i32.atomic.rmw.xor + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3a" ;; i32.atomic.rmw.xor + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3a" ;; i32.atomic.rmw.xor + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3a" ;; i32.atomic.rmw.xor + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3a" ;; i32.atomic.rmw.xor + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3a" ;; i32.atomic.rmw.xor + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3a" ;; i32.atomic.rmw.xor + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3a" ;; i32.atomic.rmw.xor + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3a" ;; i32.atomic.rmw.xor + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3b" ;; i64.atomic.rmw.xor + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3b" ;; i64.atomic.rmw.xor + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3b" ;; i64.atomic.rmw.xor + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3b" ;; i64.atomic.rmw.xor + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3b" ;; i64.atomic.rmw.xor + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3b" ;; i64.atomic.rmw.xor + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3b" ;; i64.atomic.rmw.xor + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3b" ;; i64.atomic.rmw.xor + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3b" ;; i64.atomic.rmw.xor + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3c" ;; i32.atomic.rmw8.xor_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3c" ;; i32.atomic.rmw8.xor_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3c" ;; i32.atomic.rmw8.xor_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3c" ;; i32.atomic.rmw8.xor_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3c" ;; i32.atomic.rmw8.xor_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3c" ;; i32.atomic.rmw8.xor_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3c" ;; i32.atomic.rmw8.xor_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3c" ;; i32.atomic.rmw8.xor_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3c" ;; i32.atomic.rmw8.xor_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3d" ;; i32.atomic.rmw16.xor_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3d" ;; i32.atomic.rmw16.xor_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3d" ;; i32.atomic.rmw16.xor_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3d" ;; i32.atomic.rmw16.xor_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3d" ;; i32.atomic.rmw16.xor_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3d" ;; i32.atomic.rmw16.xor_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3d" ;; i32.atomic.rmw16.xor_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3d" ;; i32.atomic.rmw16.xor_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\3d" ;; i32.atomic.rmw16.xor_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3e" ;; i64.atomic.rmw8.xor_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3e" ;; i64.atomic.rmw8.xor_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3e" ;; i64.atomic.rmw8.xor_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3e" ;; i64.atomic.rmw8.xor_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3e" ;; i64.atomic.rmw8.xor_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3e" ;; i64.atomic.rmw8.xor_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3e" ;; i64.atomic.rmw8.xor_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3e" ;; i64.atomic.rmw8.xor_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3e" ;; i64.atomic.rmw8.xor_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3f" ;; i64.atomic.rmw16.xor_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3f" ;; i64.atomic.rmw16.xor_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3f" ;; i64.atomic.rmw16.xor_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3f" ;; i64.atomic.rmw16.xor_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3f" ;; i64.atomic.rmw16.xor_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3f" ;; i64.atomic.rmw16.xor_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3f" ;; i64.atomic.rmw16.xor_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3f" ;; i64.atomic.rmw16.xor_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\3f" ;; i64.atomic.rmw16.xor_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\40" ;; i64.atomic.rmw32.xor_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\40" ;; i64.atomic.rmw32.xor_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\40" ;; i64.atomic.rmw32.xor_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\40" ;; i64.atomic.rmw32.xor_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\40" ;; i64.atomic.rmw32.xor_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\40" ;; i64.atomic.rmw32.xor_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\40" ;; i64.atomic.rmw32.xor_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\40" ;; i64.atomic.rmw32.xor_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\40" ;; i64.atomic.rmw32.xor_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\0b" ;; end +) diff --git a/test/spec/relaxed-atomics2.wast b/test/spec/relaxed-atomics2.wast deleted file mode 100644 index 39d7519a859..00000000000 --- a/test/spec/relaxed-atomics2.wast +++ /dev/null @@ -1,331 +0,0 @@ -;; Generated by scripts/test/generate-atomic-spec-test.py. Do not edit manually. - -(module - (memory i32 1 1) - (memory i64 1 1) - - ;; Memory index must come before memory ordering if present. - ;; Both immediates are optional; an ommitted memory ordering will be treated as seqcst. - (func $test-all-ops - (drop (i32.atomic.load (i32.const 42))) - (drop (i32.atomic.load acqrel (i32.const 42))) - (drop (i32.atomic.load seqcst (i32.const 42))) - (drop (i32.atomic.load 0 (i32.const 42))) - (drop (i32.atomic.load 0 acqrel (i32.const 42))) - (drop (i32.atomic.load 0 seqcst (i32.const 42))) - (drop (i32.atomic.load 1 (i64.const 42))) - (drop (i32.atomic.load 1 acqrel (i64.const 42))) - (drop (i32.atomic.load 1 seqcst (i64.const 42))) - (drop (i64.atomic.load (i32.const 42))) - (drop (i64.atomic.load acqrel (i32.const 42))) - (drop (i64.atomic.load seqcst (i32.const 42))) - (drop (i64.atomic.load 0 (i32.const 42))) - (drop (i64.atomic.load 0 acqrel (i32.const 42))) - (drop (i64.atomic.load 0 seqcst (i32.const 42))) - (drop (i64.atomic.load 1 (i64.const 42))) - (drop (i64.atomic.load 1 acqrel (i64.const 42))) - (drop (i64.atomic.load 1 seqcst (i64.const 42))) - (i32.atomic.store (i32.const 42) (i32.const 42)) - (i32.atomic.store acqrel (i32.const 42) (i32.const 42)) - (i32.atomic.store seqcst (i32.const 42) (i32.const 42)) - (i32.atomic.store 0 (i32.const 42) (i32.const 42)) - (i32.atomic.store 0 acqrel (i32.const 42) (i32.const 42)) - (i32.atomic.store 0 seqcst (i32.const 42) (i32.const 42)) - (i32.atomic.store 1 (i64.const 42) (i32.const 42)) - (i32.atomic.store 1 acqrel (i64.const 42) (i32.const 42)) - (i32.atomic.store 1 seqcst (i64.const 42) (i32.const 42)) - (i64.atomic.store (i32.const 42) (i64.const 42)) - (i64.atomic.store acqrel (i32.const 42) (i64.const 42)) - (i64.atomic.store seqcst (i32.const 42) (i64.const 42)) - (i64.atomic.store 0 (i32.const 42) (i64.const 42)) - (i64.atomic.store 0 acqrel (i32.const 42) (i64.const 42)) - (i64.atomic.store 0 seqcst (i32.const 42) (i64.const 42)) - (i64.atomic.store 1 (i64.const 42) (i64.const 42)) - (i64.atomic.store 1 acqrel (i64.const 42) (i64.const 42)) - (i64.atomic.store 1 seqcst (i64.const 42) (i64.const 42)) - ) -) - -(assert_invalid (module - (memory 1 1 shared) - - (func $i32load (drop (i32.load acqrel (i32.const 51)))) -) "Can't set memory ordering for non-atomic i32.load") - -(module binary - "\00asm\01\00\00\00" ;; Wasm header - "\01\04\01" ;; Type section - "\60\00\00" ;; $test-all-ops type - "\03\02\01\00" ;; Function section - "\05\07\02" ;; Memory section - "\01\01\01" ;; (memory i32 1 1) - "\05\01\01" ;; (memory i64 1 1) - "\0a\c3\02\01" ;; Code section - "\c0\02\00" ;; func $test-all-ops - - "\41\33" ;; (i32.const 51) - "\fe\10" ;; i32.atomic.load - "\02" ;; Alignment of 2 - "\00" ;; offset - "\1a" ;; drop - - "\41\33" ;; (i32.const 51) - "\fe\10" ;; i32.atomic.load - "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows - "\01" ;; acqrel memory ordering - "\00" ;; offset - "\1a" ;; drop - - "\41\33" ;; (i32.const 51) - "\fe\10" ;; i32.atomic.load - "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows - "\00" ;; seqcst memory ordering - "\00" ;; offset - "\1a" ;; drop - - "\41\33" ;; (i32.const 51) - "\fe\10" ;; i32.atomic.load - "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows - "\00" ;; memory index - "\00" ;; offset - "\1a" ;; drop - - "\41\33" ;; (i32.const 51) - "\fe\10" ;; i32.atomic.load - "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows - "\00" ;; memory index - "\01" ;; acqrel memory ordering - "\00" ;; offset - "\1a" ;; drop - - "\41\33" ;; (i32.const 51) - "\fe\10" ;; i32.atomic.load - "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows - "\00" ;; memory index - "\00" ;; seqcst memory ordering - "\00" ;; offset - "\1a" ;; drop - - "\42\33" ;; (i64.const 51) - "\fe\10" ;; i32.atomic.load - "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows - "\01" ;; memory index - "\00" ;; offset - "\1a" ;; drop - - "\42\33" ;; (i64.const 51) - "\fe\10" ;; i32.atomic.load - "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows - "\01" ;; memory index - "\01" ;; acqrel memory ordering - "\00" ;; offset - "\1a" ;; drop - - "\42\33" ;; (i64.const 51) - "\fe\10" ;; i32.atomic.load - "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows - "\01" ;; memory index - "\00" ;; seqcst memory ordering - "\00" ;; offset - "\1a" ;; drop - - "\41\33" ;; (i32.const 51) - "\fe\11" ;; i64.atomic.load - "\02" ;; Alignment of 2 - "\00" ;; offset - "\1a" ;; drop - - "\41\33" ;; (i32.const 51) - "\fe\11" ;; i64.atomic.load - "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows - "\01" ;; acqrel memory ordering - "\00" ;; offset - "\1a" ;; drop - - "\41\33" ;; (i32.const 51) - "\fe\11" ;; i64.atomic.load - "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows - "\00" ;; seqcst memory ordering - "\00" ;; offset - "\1a" ;; drop - - "\41\33" ;; (i32.const 51) - "\fe\11" ;; i64.atomic.load - "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows - "\00" ;; memory index - "\00" ;; offset - "\1a" ;; drop - - "\41\33" ;; (i32.const 51) - "\fe\11" ;; i64.atomic.load - "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows - "\00" ;; memory index - "\01" ;; acqrel memory ordering - "\00" ;; offset - "\1a" ;; drop - - "\41\33" ;; (i32.const 51) - "\fe\11" ;; i64.atomic.load - "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows - "\00" ;; memory index - "\00" ;; seqcst memory ordering - "\00" ;; offset - "\1a" ;; drop - - "\42\33" ;; (i64.const 51) - "\fe\11" ;; i64.atomic.load - "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows - "\01" ;; memory index - "\00" ;; offset - "\1a" ;; drop - - "\42\33" ;; (i64.const 51) - "\fe\11" ;; i64.atomic.load - "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows - "\01" ;; memory index - "\01" ;; acqrel memory ordering - "\00" ;; offset - "\1a" ;; drop - - "\42\33" ;; (i64.const 51) - "\fe\11" ;; i64.atomic.load - "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows - "\01" ;; memory index - "\00" ;; seqcst memory ordering - "\00" ;; offset - "\1a" ;; drop - - "\41\33" ;; (i32.const 51) - "\41\33" ;; (i32.const 51) - "\fe\17" ;; i32.atomic.store - "\02" ;; Alignment of 2 - "\00" ;; offset - - "\41\33" ;; (i32.const 51) - "\41\33" ;; (i32.const 51) - "\fe\17" ;; i32.atomic.store - "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows - "\01" ;; acqrel memory ordering - "\00" ;; offset - - "\41\33" ;; (i32.const 51) - "\41\33" ;; (i32.const 51) - "\fe\17" ;; i32.atomic.store - "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows - "\00" ;; seqcst memory ordering - "\00" ;; offset - - "\41\33" ;; (i32.const 51) - "\41\33" ;; (i32.const 51) - "\fe\17" ;; i32.atomic.store - "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows - "\00" ;; memory index - "\00" ;; offset - - "\41\33" ;; (i32.const 51) - "\41\33" ;; (i32.const 51) - "\fe\17" ;; i32.atomic.store - "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows - "\00" ;; memory index - "\01" ;; acqrel memory ordering - "\00" ;; offset - - "\41\33" ;; (i32.const 51) - "\41\33" ;; (i32.const 51) - "\fe\17" ;; i32.atomic.store - "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows - "\00" ;; memory index - "\00" ;; seqcst memory ordering - "\00" ;; offset - - "\42\33" ;; (i64.const 51) - "\41\33" ;; (i32.const 51) - "\fe\17" ;; i32.atomic.store - "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows - "\01" ;; memory index - "\00" ;; offset - - "\42\33" ;; (i64.const 51) - "\41\33" ;; (i32.const 51) - "\fe\17" ;; i32.atomic.store - "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows - "\01" ;; memory index - "\01" ;; acqrel memory ordering - "\00" ;; offset - - "\42\33" ;; (i64.const 51) - "\41\33" ;; (i32.const 51) - "\fe\17" ;; i32.atomic.store - "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows - "\01" ;; memory index - "\00" ;; seqcst memory ordering - "\00" ;; offset - - "\41\33" ;; (i32.const 51) - "\42\33" ;; (i64.const 51) - "\fe\18" ;; i64.atomic.store - "\02" ;; Alignment of 2 - "\00" ;; offset - - "\41\33" ;; (i32.const 51) - "\42\33" ;; (i64.const 51) - "\fe\18" ;; i64.atomic.store - "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows - "\01" ;; acqrel memory ordering - "\00" ;; offset - - "\41\33" ;; (i32.const 51) - "\42\33" ;; (i64.const 51) - "\fe\18" ;; i64.atomic.store - "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows - "\00" ;; seqcst memory ordering - "\00" ;; offset - - "\41\33" ;; (i32.const 51) - "\42\33" ;; (i64.const 51) - "\fe\18" ;; i64.atomic.store - "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows - "\00" ;; memory index - "\00" ;; offset - - "\41\33" ;; (i32.const 51) - "\42\33" ;; (i64.const 51) - "\fe\18" ;; i64.atomic.store - "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows - "\00" ;; memory index - "\01" ;; acqrel memory ordering - "\00" ;; offset - - "\41\33" ;; (i32.const 51) - "\42\33" ;; (i64.const 51) - "\fe\18" ;; i64.atomic.store - "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows - "\00" ;; memory index - "\00" ;; seqcst memory ordering - "\00" ;; offset - - "\42\33" ;; (i64.const 51) - "\42\33" ;; (i64.const 51) - "\fe\18" ;; i64.atomic.store - "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows - "\01" ;; memory index - "\00" ;; offset - - "\42\33" ;; (i64.const 51) - "\42\33" ;; (i64.const 51) - "\fe\18" ;; i64.atomic.store - "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows - "\01" ;; memory index - "\01" ;; acqrel memory ordering - "\00" ;; offset - - "\42\33" ;; (i64.const 51) - "\42\33" ;; (i64.const 51) - "\fe\18" ;; i64.atomic.store - "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows - "\01" ;; memory index - "\00" ;; seqcst memory ordering - "\00" ;; offset - - "\0b" ;; end -) From dda4c5c616e40226a940d44a385bd12f28f5d5df Mon Sep 17 00:00:00 2001 From: stevenfontanella Date: Fri, 23 Jan 2026 21:10:51 +0000 Subject: [PATCH 2/2] Memory order for compoare-exchange --- scripts/test/generate-atomic-spec-test.py | 14 + src/binaryen-c.cpp | 18 +- src/ir/properties.h | 3 + src/parser/contexts.h | 16 +- src/parser/parsers.h | 13 +- src/passes/Print.cpp | 1 + src/tools/fuzzing/fuzzing.cpp | 10 +- src/wasm-builder.h | 6 +- src/wasm-delegations-fields.def | 1 + src/wasm-ir-builder.h | 4 +- src/wasm.h | 1 + src/wasm/wasm-binary.cpp | 21 +- src/wasm/wasm-ir-builder.cpp | 16 +- src/wasm/wasm-stack.cpp | 2 +- src/wasm/wasm-validator.cpp | 22 + test/spec/relaxed-atomics.wast | 1243 ++++++++++++++++++++- 16 files changed, 1353 insertions(+), 38 deletions(-) diff --git a/scripts/test/generate-atomic-spec-test.py b/scripts/test/generate-atomic-spec-test.py index c67fae9d299..6c4c53990d3 100644 --- a/scripts/test/generate-atomic-spec-test.py +++ b/scripts/test/generate-atomic-spec-test.py @@ -86,6 +86,20 @@ class Template: Template(op="i64.atomic.rmw8.xor_u", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x3e"), Template(op="i64.atomic.rmw16.xor_u", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x3f"), Template(op="i64.atomic.rmw32.xor_u", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x40"), + Template(op="i32.atomic.rmw.xchg", value_type=ValueType.i32, args=2, should_drop=True, bin=b"\xfe\x41"), + Template(op="i64.atomic.rmw.xchg", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x42"), + Template(op="i32.atomic.rmw8.xchg_u", value_type=ValueType.i32, args=2, should_drop=True, bin=b"\xfe\x43"), + Template(op="i32.atomic.rmw16.xchg_u", value_type=ValueType.i32, args=2, should_drop=True, bin=b"\xfe\x44"), + Template(op="i64.atomic.rmw8.xchg_u", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x45"), + Template(op="i64.atomic.rmw16.xchg_u", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x46"), + Template(op="i64.atomic.rmw32.xchg_u", value_type=ValueType.i64, args=2, should_drop=True, bin=b"\xfe\x47"), + Template(op="i32.atomic.rmw.cmpxchg", value_type=ValueType.i32, args=3, should_drop=True, bin=b"\xfe\x48"), + Template(op="i64.atomic.rmw.cmpxchg", value_type=ValueType.i64, args=3, should_drop=True, bin=b"\xfe\x49"), + Template(op="i32.atomic.rmw8.cmpxchg_u", value_type=ValueType.i32, args=3, should_drop=True, bin=b"\xfe\x4a"), + Template(op="i32.atomic.rmw16.cmpxchg_u", value_type=ValueType.i32, args=3, should_drop=True, bin=b"\xfe\x4b"), + Template(op="i64.atomic.rmw8.cmpxchg_u", value_type=ValueType.i64, args=3, should_drop=True, bin=b"\xfe\x4c"), + Template(op="i64.atomic.rmw16.cmpxchg_u", value_type=ValueType.i64, args=3, should_drop=True, bin=b"\xfe\x4d"), + Template(op="i64.atomic.rmw32.cmpxchg_u", value_type=ValueType.i64, args=3, should_drop=True, bin=b"\xfe\x4e"), ] diff --git a/src/binaryen-c.cpp b/src/binaryen-c.cpp index 50d83a5b1fc..825ea59326e 100644 --- a/src/binaryen-c.cpp +++ b/src/binaryen-c.cpp @@ -1400,15 +1400,15 @@ BinaryenExpressionRef BinaryenAtomicCmpxchg(BinaryenModuleRef module, BinaryenExpressionRef replacement, BinaryenType type, const char* memoryName) { - return static_cast( - Builder(*(Module*)module) - .makeAtomicCmpxchg(bytes, - offset, - (Expression*)ptr, - (Expression*)expected, - (Expression*)replacement, - Type(type), - getMemoryName(module, memoryName))); + return Builder(*(Module*)module) + .makeAtomicCmpxchg(bytes, + offset, + (Expression*)ptr, + (Expression*)expected, + (Expression*)replacement, + Type(type), + getMemoryName(module, memoryName), + MemoryOrder::SeqCst); } BinaryenExpressionRef BinaryenAtomicWait(BinaryenModuleRef module, BinaryenExpressionRef ptr, diff --git a/src/ir/properties.h b/src/ir/properties.h index e28a519e540..e763ccd9098 100644 --- a/src/ir/properties.h +++ b/src/ir/properties.h @@ -510,6 +510,9 @@ inline MemoryOrder getMemoryOrder(Expression* curr) { if (auto* rmw = curr->dynCast()) { return rmw->order; } + if (auto* cmpxchg = curr->dynCast()) { + return cmpxchg->order; + } if (curr->is() || curr->is() || curr->is()) { return MemoryOrder::SeqCst; diff --git a/src/parser/contexts.h b/src/parser/contexts.h index 82083ca82ed..9e9483cbd4c 100644 --- a/src/parser/contexts.h +++ b/src/parser/contexts.h @@ -579,8 +579,13 @@ struct NullInstrParserCtx { MemoryOrder) { return Ok{}; } - Result<> makeAtomicCmpxchg( - Index, const std::vector&, Type, int, MemoryIdxT*, MemargT) { + Result<> makeAtomicCmpxchg(Index, + const std::vector&, + Type, + int, + MemoryIdxT*, + MemargT, + MemoryOrder) { return Ok{}; } Result<> makeAtomicWait( @@ -2288,11 +2293,12 @@ struct ParseDefsCtx : TypeParserCtx, AnnotationParserCtx { Type type, int bytes, Name* mem, - Memarg memarg) { + Memarg memarg, + MemoryOrder order) { auto m = getMemory(pos, mem); CHECK_ERR(m); - return withLoc(pos, - irBuilder.makeAtomicCmpxchg(bytes, memarg.offset, type, *m)); + return withLoc( + pos, irBuilder.makeAtomicCmpxchg(bytes, memarg.offset, type, *m, order)); } Result<> makeAtomicWait(Index pos, diff --git a/src/parser/parsers.h b/src/parser/parsers.h index b1eb6c71b9d..d606563f1c1 100644 --- a/src/parser/parsers.h +++ b/src/parser/parsers.h @@ -1839,10 +1839,19 @@ Result<> makeAtomicCmpxchg(Ctx& ctx, uint8_t bytes) { auto mem = maybeMemidx(ctx); CHECK_ERR(mem); + + auto maybeOrder = maybeMemOrder(ctx); + CHECK_ERR(maybeOrder); + auto arg = memarg(ctx, bytes); CHECK_ERR(arg); - return ctx.makeAtomicCmpxchg( - pos, annotations, type, bytes, mem.getPtr(), *arg); + return ctx.makeAtomicCmpxchg(pos, + annotations, + type, + bytes, + mem.getPtr(), + *arg, + maybeOrder ? *maybeOrder : MemoryOrder::SeqCst); } template diff --git a/src/passes/Print.cpp b/src/passes/Print.cpp index 380c2db4629..f0180832949 100644 --- a/src/passes/Print.cpp +++ b/src/passes/Print.cpp @@ -676,6 +676,7 @@ struct PrintExpressionContents } restoreNormalColor(o); printMemoryName(curr->memory, o, wasm); + printMemoryOrder(curr->order); if (curr->offset) { o << " offset=" << curr->offset; } diff --git a/src/tools/fuzzing/fuzzing.cpp b/src/tools/fuzzing/fuzzing.cpp index 1aeaf9c8576..9f982ce4521 100644 --- a/src/tools/fuzzing/fuzzing.cpp +++ b/src/tools/fuzzing/fuzzing.cpp @@ -4775,8 +4775,14 @@ Expression* TranslateToFuzzReader::makeAtomic(Type type) { } else { auto* expected = make(type); auto* replacement = make(type); - return builder.makeAtomicCmpxchg( - bytes, offset, ptr, expected, replacement, type, wasm.memories[0]->name); + return builder.makeAtomicCmpxchg(bytes, + offset, + ptr, + expected, + replacement, + type, + wasm.memories[0]->name, + MemoryOrder::SeqCst); } } diff --git a/src/wasm-builder.h b/src/wasm-builder.h index 0d09fa661a1..29c9e342729 100644 --- a/src/wasm-builder.h +++ b/src/wasm-builder.h @@ -486,7 +486,8 @@ class Builder { Expression* expected, Expression* replacement, Type type, - Name memory) { + Name memory, + MemoryOrder order) { auto* ret = wasm.allocator.alloc(); ret->bytes = bytes; ret->offset = offset; @@ -494,8 +495,9 @@ class Builder { ret->expected = expected; ret->replacement = replacement; ret->type = type; - ret->finalize(); ret->memory = memory; + ret->order = order; + ret->finalize(); return ret; } SIMDExtract* diff --git a/src/wasm-delegations-fields.def b/src/wasm-delegations-fields.def index 143528b769e..895fa8b9276 100644 --- a/src/wasm-delegations-fields.def +++ b/src/wasm-delegations-fields.def @@ -385,6 +385,7 @@ DELEGATE_FIELD_CHILD(AtomicCmpxchg, expected) DELEGATE_FIELD_CHILD(AtomicCmpxchg, ptr) DELEGATE_FIELD_INT(AtomicCmpxchg, bytes) DELEGATE_FIELD_ADDRESS(AtomicCmpxchg, offset) +DELEGATE_FIELD_INT(AtomicCmpxchg, order) DELEGATE_FIELD_NAME_KIND(AtomicCmpxchg, memory, ModuleItemKind::Memory) DELEGATE_FIELD_CASE_END(AtomicCmpxchg) diff --git a/src/wasm-ir-builder.h b/src/wasm-ir-builder.h index 5f06ddd9b39..6ace5587b53 100644 --- a/src/wasm-ir-builder.h +++ b/src/wasm-ir-builder.h @@ -166,8 +166,8 @@ class IRBuilder : public UnifiedExpressionVisitor> { Type type, Name mem, MemoryOrder order); - Result<> - makeAtomicCmpxchg(unsigned bytes, Address offset, Type type, Name mem); + Result<> makeAtomicCmpxchg( + unsigned bytes, Address offset, Type type, Name mem, MemoryOrder order); Result<> makeAtomicWait(Type type, Address offset, Name mem); Result<> makeAtomicNotify(Address offset, Name mem); Result<> makeAtomicFence(); diff --git a/src/wasm.h b/src/wasm.h index 373f935b918..ed81662963e 100644 --- a/src/wasm.h +++ b/src/wasm.h @@ -1051,6 +1051,7 @@ class AtomicCmpxchg : public SpecificExpression { Expression* expected; Expression* replacement; Name memory; + MemoryOrder order = MemoryOrder::SeqCst; void finalize(); }; diff --git a/src/wasm/wasm-binary.cpp b/src/wasm/wasm-binary.cpp index 1aa002f4e03..10297f42367 100644 --- a/src/wasm/wasm-binary.cpp +++ b/src/wasm/wasm-binary.cpp @@ -3747,31 +3747,38 @@ Result<> WasmBinaryReader::readInst() { case BinaryConsts::I32AtomicCmpxchg: { auto [mem, align, offset, memoryOrder] = getRMWMemarg(); - return builder.makeAtomicCmpxchg(4, offset, Type::i32, mem); + return builder.makeAtomicCmpxchg( + 4, offset, Type::i32, mem, memoryOrder); } case BinaryConsts::I32AtomicCmpxchg8U: { auto [mem, align, offset, memoryOrder] = getRMWMemarg(); - return builder.makeAtomicCmpxchg(1, offset, Type::i32, mem); + return builder.makeAtomicCmpxchg( + 1, offset, Type::i32, mem, memoryOrder); } case BinaryConsts::I32AtomicCmpxchg16U: { auto [mem, align, offset, memoryOrder] = getRMWMemarg(); - return builder.makeAtomicCmpxchg(2, offset, Type::i32, mem); + return builder.makeAtomicCmpxchg( + 2, offset, Type::i32, mem, memoryOrder); } case BinaryConsts::I64AtomicCmpxchg: { auto [mem, align, offset, memoryOrder] = getRMWMemarg(); - return builder.makeAtomicCmpxchg(8, offset, Type::i64, mem); + return builder.makeAtomicCmpxchg( + 8, offset, Type::i64, mem, memoryOrder); } case BinaryConsts::I64AtomicCmpxchg8U: { auto [mem, align, offset, memoryOrder] = getRMWMemarg(); - return builder.makeAtomicCmpxchg(1, offset, Type::i64, mem); + return builder.makeAtomicCmpxchg( + 1, offset, Type::i64, mem, memoryOrder); } case BinaryConsts::I64AtomicCmpxchg16U: { auto [mem, align, offset, memoryOrder] = getRMWMemarg(); - return builder.makeAtomicCmpxchg(2, offset, Type::i64, mem); + return builder.makeAtomicCmpxchg( + 2, offset, Type::i64, mem, memoryOrder); } case BinaryConsts::I64AtomicCmpxchg32U: { auto [mem, align, offset, memoryOrder] = getRMWMemarg(); - return builder.makeAtomicCmpxchg(4, offset, Type::i64, mem); + return builder.makeAtomicCmpxchg( + 4, offset, Type::i64, mem, memoryOrder); } case BinaryConsts::I32AtomicWait: { auto [mem, align, offset, memoryOrder] = getAtomicMemarg(); diff --git a/src/wasm/wasm-ir-builder.cpp b/src/wasm/wasm-ir-builder.cpp index 0144c8d1ea6..703c33a6bcd 100644 --- a/src/wasm/wasm-ir-builder.cpp +++ b/src/wasm/wasm-ir-builder.cpp @@ -1518,15 +1518,19 @@ Result<> IRBuilder::makeAtomicRMW(AtomicRMWOp op, return Ok{}; } -Result<> IRBuilder::makeAtomicCmpxchg(unsigned bytes, - Address offset, - Type type, - Name mem) { +Result<> IRBuilder::makeAtomicCmpxchg( + unsigned bytes, Address offset, Type type, Name mem, MemoryOrder order) { AtomicCmpxchg curr; curr.memory = mem; CHECK_ERR(ChildPopper{*this}.visitAtomicCmpxchg(&curr, type)); - push(builder.makeAtomicCmpxchg( - bytes, offset, curr.ptr, curr.expected, curr.replacement, type, mem)); + push(builder.makeAtomicCmpxchg(bytes, + offset, + curr.ptr, + curr.expected, + curr.replacement, + type, + mem, + order)); return Ok{}; } diff --git a/src/wasm/wasm-stack.cpp b/src/wasm/wasm-stack.cpp index 5d6302596fa..d070f5c3ed3 100644 --- a/src/wasm/wasm-stack.cpp +++ b/src/wasm/wasm-stack.cpp @@ -587,7 +587,7 @@ void BinaryInstWriter::visitAtomicCmpxchg(AtomicCmpxchg* curr) { curr->bytes, curr->offset, curr->memory, - MemoryOrder::SeqCst, + curr->order, /*isRMW=*/true); } diff --git a/src/wasm/wasm-validator.cpp b/src/wasm/wasm-validator.cpp index f50a51f6f55..4b579865d5d 100644 --- a/src/wasm/wasm-validator.cpp +++ b/src/wasm/wasm-validator.cpp @@ -1238,6 +1238,28 @@ void FunctionValidator::visitAtomicCmpxchg(AtomicCmpxchg* curr) { shouldBeTrue(getModule()->features.hasAtomics(), curr, "Atomic operations require threads [--enable-threads]"); + + switch (curr->order) { + case MemoryOrder::AcqRel: { + shouldBeTrue(getModule()->features.hasRelaxedAtomics(), + curr, + "Acquire/release operations require relaxed atomics " + "[--enable-relaxed-atomics]"); + break; + } + // Unordered cmpxchg should be impossible unless there's a bug in the + // parser. + case MemoryOrder::Unordered: { + shouldBeUnequal(curr->order, + MemoryOrder::Unordered, + curr, + "Atomic cmpxchg can't be unordered"); + break; + } + case MemoryOrder::SeqCst: + break; + } + validateMemBytes(curr->bytes, curr->type, curr); shouldBeEqualOrFirstIsUnreachable( curr->ptr->type, diff --git a/test/spec/relaxed-atomics.wast b/test/spec/relaxed-atomics.wast index c7d307a90d7..0afe492d07e 100644 --- a/test/spec/relaxed-atomics.wast +++ b/test/spec/relaxed-atomics.wast @@ -448,6 +448,132 @@ (drop (i64.atomic.rmw32.xor_u 1 (i64.const 42) (i64.const 42))) (drop (i64.atomic.rmw32.xor_u 1 acqrel (i64.const 42) (i64.const 42))) (drop (i64.atomic.rmw32.xor_u 1 seqcst (i64.const 42) (i64.const 42))) + (drop (i32.atomic.rmw.xchg (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.xchg acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.xchg seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.xchg 0 (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.xchg 0 acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.xchg 0 seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.xchg 1 (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.xchg 1 acqrel (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.xchg 1 seqcst (i64.const 42) (i32.const 42))) + (drop (i64.atomic.rmw.xchg (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.xchg acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.xchg seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.xchg 0 (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.xchg 0 acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.xchg 0 seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.xchg 1 (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.xchg 1 acqrel (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.xchg 1 seqcst (i64.const 42) (i64.const 42))) + (drop (i32.atomic.rmw8.xchg_u (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.xchg_u acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.xchg_u seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.xchg_u 0 (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.xchg_u 0 acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.xchg_u 0 seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.xchg_u 1 (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.xchg_u 1 acqrel (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.xchg_u 1 seqcst (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.xchg_u (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.xchg_u acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.xchg_u seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.xchg_u 0 (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.xchg_u 0 acqrel (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.xchg_u 0 seqcst (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.xchg_u 1 (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.xchg_u 1 acqrel (i64.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.xchg_u 1 seqcst (i64.const 42) (i32.const 42))) + (drop (i64.atomic.rmw8.xchg_u (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.xchg_u acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.xchg_u seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.xchg_u 0 (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.xchg_u 0 acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.xchg_u 0 seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.xchg_u 1 (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.xchg_u 1 acqrel (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.xchg_u 1 seqcst (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.xchg_u (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.xchg_u acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.xchg_u seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.xchg_u 0 (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.xchg_u 0 acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.xchg_u 0 seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.xchg_u 1 (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.xchg_u 1 acqrel (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.xchg_u 1 seqcst (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.xchg_u (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.xchg_u acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.xchg_u seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.xchg_u 0 (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.xchg_u 0 acqrel (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.xchg_u 0 seqcst (i32.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.xchg_u 1 (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.xchg_u 1 acqrel (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.xchg_u 1 seqcst (i64.const 42) (i64.const 42))) + (drop (i32.atomic.rmw.cmpxchg (i32.const 42) (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.cmpxchg acqrel (i32.const 42) (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.cmpxchg seqcst (i32.const 42) (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.cmpxchg 0 (i32.const 42) (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.cmpxchg 0 acqrel (i32.const 42) (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.cmpxchg 0 seqcst (i32.const 42) (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.cmpxchg 1 (i64.const 42) (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.cmpxchg 1 acqrel (i64.const 42) (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw.cmpxchg 1 seqcst (i64.const 42) (i32.const 42) (i32.const 42))) + (drop (i64.atomic.rmw.cmpxchg (i32.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.cmpxchg acqrel (i32.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.cmpxchg seqcst (i32.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.cmpxchg 0 (i32.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.cmpxchg 0 acqrel (i32.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.cmpxchg 0 seqcst (i32.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.cmpxchg 1 (i64.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.cmpxchg 1 acqrel (i64.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw.cmpxchg 1 seqcst (i64.const 42) (i64.const 42) (i64.const 42))) + (drop (i32.atomic.rmw8.cmpxchg_u (i32.const 42) (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.cmpxchg_u acqrel (i32.const 42) (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.cmpxchg_u seqcst (i32.const 42) (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.cmpxchg_u 0 (i32.const 42) (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.cmpxchg_u 0 acqrel (i32.const 42) (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.cmpxchg_u 0 seqcst (i32.const 42) (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.cmpxchg_u 1 (i64.const 42) (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.cmpxchg_u 1 acqrel (i64.const 42) (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw8.cmpxchg_u 1 seqcst (i64.const 42) (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.cmpxchg_u (i32.const 42) (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.cmpxchg_u acqrel (i32.const 42) (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.cmpxchg_u seqcst (i32.const 42) (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.cmpxchg_u 0 (i32.const 42) (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.cmpxchg_u 0 acqrel (i32.const 42) (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.cmpxchg_u 0 seqcst (i32.const 42) (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.cmpxchg_u 1 (i64.const 42) (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.cmpxchg_u 1 acqrel (i64.const 42) (i32.const 42) (i32.const 42))) + (drop (i32.atomic.rmw16.cmpxchg_u 1 seqcst (i64.const 42) (i32.const 42) (i32.const 42))) + (drop (i64.atomic.rmw8.cmpxchg_u (i32.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.cmpxchg_u acqrel (i32.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.cmpxchg_u seqcst (i32.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.cmpxchg_u 0 (i32.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.cmpxchg_u 0 acqrel (i32.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.cmpxchg_u 0 seqcst (i32.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.cmpxchg_u 1 (i64.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.cmpxchg_u 1 acqrel (i64.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw8.cmpxchg_u 1 seqcst (i64.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.cmpxchg_u (i32.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.cmpxchg_u acqrel (i32.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.cmpxchg_u seqcst (i32.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.cmpxchg_u 0 (i32.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.cmpxchg_u 0 acqrel (i32.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.cmpxchg_u 0 seqcst (i32.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.cmpxchg_u 1 (i64.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.cmpxchg_u 1 acqrel (i64.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw16.cmpxchg_u 1 seqcst (i64.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.cmpxchg_u (i32.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.cmpxchg_u acqrel (i32.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.cmpxchg_u seqcst (i32.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.cmpxchg_u 0 (i32.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.cmpxchg_u 0 acqrel (i32.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.cmpxchg_u 0 seqcst (i32.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.cmpxchg_u 1 (i64.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.cmpxchg_u 1 acqrel (i64.const 42) (i64.const 42) (i64.const 42))) + (drop (i64.atomic.rmw32.cmpxchg_u 1 seqcst (i64.const 42) (i64.const 42) (i64.const 42))) ) ) @@ -465,8 +591,8 @@ "\05\07\02" ;; Memory section "\01\01\01" ;; (memory i32 1 1) "\05\01\01" ;; (memory i64 1 1) - "\0a\95\22\01" ;; Code section - "\92\22\00" ;; func $test-all-ops + "\0a\a9\2d\01" ;; Code section + "\a6\2d\00" ;; func $test-all-ops "\41\33" ;; (i32.const 51) "\fe\10" ;; i32.atomic.load @@ -4017,5 +4143,1118 @@ "\00" ;; offset "\1a" ;; drop + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\41" ;; i32.atomic.rmw.xchg + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\41" ;; i32.atomic.rmw.xchg + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\41" ;; i32.atomic.rmw.xchg + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\41" ;; i32.atomic.rmw.xchg + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\41" ;; i32.atomic.rmw.xchg + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\41" ;; i32.atomic.rmw.xchg + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\41" ;; i32.atomic.rmw.xchg + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\41" ;; i32.atomic.rmw.xchg + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\41" ;; i32.atomic.rmw.xchg + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\42" ;; i64.atomic.rmw.xchg + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\42" ;; i64.atomic.rmw.xchg + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\42" ;; i64.atomic.rmw.xchg + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\42" ;; i64.atomic.rmw.xchg + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\42" ;; i64.atomic.rmw.xchg + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\42" ;; i64.atomic.rmw.xchg + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\42" ;; i64.atomic.rmw.xchg + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\42" ;; i64.atomic.rmw.xchg + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\42" ;; i64.atomic.rmw.xchg + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\43" ;; i32.atomic.rmw8.xchg_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\43" ;; i32.atomic.rmw8.xchg_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\43" ;; i32.atomic.rmw8.xchg_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\43" ;; i32.atomic.rmw8.xchg_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\43" ;; i32.atomic.rmw8.xchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\43" ;; i32.atomic.rmw8.xchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\43" ;; i32.atomic.rmw8.xchg_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\43" ;; i32.atomic.rmw8.xchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\43" ;; i32.atomic.rmw8.xchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\44" ;; i32.atomic.rmw16.xchg_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\44" ;; i32.atomic.rmw16.xchg_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\44" ;; i32.atomic.rmw16.xchg_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\44" ;; i32.atomic.rmw16.xchg_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\44" ;; i32.atomic.rmw16.xchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\44" ;; i32.atomic.rmw16.xchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\44" ;; i32.atomic.rmw16.xchg_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\44" ;; i32.atomic.rmw16.xchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\fe\44" ;; i32.atomic.rmw16.xchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\45" ;; i64.atomic.rmw8.xchg_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\45" ;; i64.atomic.rmw8.xchg_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\45" ;; i64.atomic.rmw8.xchg_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\45" ;; i64.atomic.rmw8.xchg_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\45" ;; i64.atomic.rmw8.xchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\45" ;; i64.atomic.rmw8.xchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\45" ;; i64.atomic.rmw8.xchg_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\45" ;; i64.atomic.rmw8.xchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\45" ;; i64.atomic.rmw8.xchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\46" ;; i64.atomic.rmw16.xchg_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\46" ;; i64.atomic.rmw16.xchg_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\46" ;; i64.atomic.rmw16.xchg_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\46" ;; i64.atomic.rmw16.xchg_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\46" ;; i64.atomic.rmw16.xchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\46" ;; i64.atomic.rmw16.xchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\46" ;; i64.atomic.rmw16.xchg_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\46" ;; i64.atomic.rmw16.xchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\46" ;; i64.atomic.rmw16.xchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\47" ;; i64.atomic.rmw32.xchg_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\47" ;; i64.atomic.rmw32.xchg_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\47" ;; i64.atomic.rmw32.xchg_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\47" ;; i64.atomic.rmw32.xchg_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\47" ;; i64.atomic.rmw32.xchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\fe\47" ;; i64.atomic.rmw32.xchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\47" ;; i64.atomic.rmw32.xchg_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\47" ;; i64.atomic.rmw32.xchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\47" ;; i64.atomic.rmw32.xchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\48" ;; i32.atomic.rmw.cmpxchg + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\48" ;; i32.atomic.rmw.cmpxchg + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\48" ;; i32.atomic.rmw.cmpxchg + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\48" ;; i32.atomic.rmw.cmpxchg + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\48" ;; i32.atomic.rmw.cmpxchg + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\48" ;; i32.atomic.rmw.cmpxchg + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\48" ;; i32.atomic.rmw.cmpxchg + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\48" ;; i32.atomic.rmw.cmpxchg + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\48" ;; i32.atomic.rmw.cmpxchg + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\49" ;; i64.atomic.rmw.cmpxchg + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\49" ;; i64.atomic.rmw.cmpxchg + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\49" ;; i64.atomic.rmw.cmpxchg + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\49" ;; i64.atomic.rmw.cmpxchg + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\49" ;; i64.atomic.rmw.cmpxchg + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\49" ;; i64.atomic.rmw.cmpxchg + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\49" ;; i64.atomic.rmw.cmpxchg + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\49" ;; i64.atomic.rmw.cmpxchg + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\49" ;; i64.atomic.rmw.cmpxchg + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\4a" ;; i32.atomic.rmw8.cmpxchg_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\4a" ;; i32.atomic.rmw8.cmpxchg_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\4a" ;; i32.atomic.rmw8.cmpxchg_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\4a" ;; i32.atomic.rmw8.cmpxchg_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\4a" ;; i32.atomic.rmw8.cmpxchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\4a" ;; i32.atomic.rmw8.cmpxchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\4a" ;; i32.atomic.rmw8.cmpxchg_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\4a" ;; i32.atomic.rmw8.cmpxchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\4a" ;; i32.atomic.rmw8.cmpxchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\4b" ;; i32.atomic.rmw16.cmpxchg_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\4b" ;; i32.atomic.rmw16.cmpxchg_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\4b" ;; i32.atomic.rmw16.cmpxchg_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\4b" ;; i32.atomic.rmw16.cmpxchg_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\4b" ;; i32.atomic.rmw16.cmpxchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\4b" ;; i32.atomic.rmw16.cmpxchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\4b" ;; i32.atomic.rmw16.cmpxchg_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\4b" ;; i32.atomic.rmw16.cmpxchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\41\33" ;; (i32.const 51) + "\41\33" ;; (i32.const 51) + "\fe\4b" ;; i32.atomic.rmw16.cmpxchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4c" ;; i64.atomic.rmw8.cmpxchg_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4c" ;; i64.atomic.rmw8.cmpxchg_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4c" ;; i64.atomic.rmw8.cmpxchg_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4c" ;; i64.atomic.rmw8.cmpxchg_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4c" ;; i64.atomic.rmw8.cmpxchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4c" ;; i64.atomic.rmw8.cmpxchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4c" ;; i64.atomic.rmw8.cmpxchg_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4c" ;; i64.atomic.rmw8.cmpxchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4c" ;; i64.atomic.rmw8.cmpxchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4d" ;; i64.atomic.rmw16.cmpxchg_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4d" ;; i64.atomic.rmw16.cmpxchg_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4d" ;; i64.atomic.rmw16.cmpxchg_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4d" ;; i64.atomic.rmw16.cmpxchg_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4d" ;; i64.atomic.rmw16.cmpxchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4d" ;; i64.atomic.rmw16.cmpxchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4d" ;; i64.atomic.rmw16.cmpxchg_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4d" ;; i64.atomic.rmw16.cmpxchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4d" ;; i64.atomic.rmw16.cmpxchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4e" ;; i64.atomic.rmw32.cmpxchg_u + "\02" ;; Alignment of 2 + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4e" ;; i64.atomic.rmw32.cmpxchg_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4e" ;; i64.atomic.rmw32.cmpxchg_u + "\22" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4e" ;; i64.atomic.rmw32.cmpxchg_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4e" ;; i64.atomic.rmw32.cmpxchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\41\33" ;; (i32.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4e" ;; i64.atomic.rmw32.cmpxchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\00" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4e" ;; i64.atomic.rmw32.cmpxchg_u + "\42" ;; Alignment of 2 with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4e" ;; i64.atomic.rmw32.cmpxchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\11" ;; acqrel memory ordering + "\00" ;; offset + "\1a" ;; drop + + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\42\33" ;; (i64.const 51) + "\fe\4e" ;; i64.atomic.rmw32.cmpxchg_u + "\62" ;; Alignment of 2 with bit 5 set indicating that an ordering immediate follows and with bit 6 set indicating that a memory index immediate follows + "\01" ;; memory index + "\00" ;; seqcst memory ordering + "\00" ;; offset + "\1a" ;; drop + "\0b" ;; end )